Compaq iPAQ 1.0 - List of Figures

Technical Reference Guide
Compaq iPAQ Series of Desktop Personal Computers
Second Edition - February 2001
vii
LIST OF FIGURES
F
IGURE
2–1. C
OMPAQ I
PAQ D
ESKTOP
P
ERSONAL
C
OMPUTERS
................................................................. 2-1
F
IGURE
2–2. C
OMPAQ I
PAQ D
ESKTOPS
, F
RONT
V
IEWS
............................................................................. 2-4
F
IGURE
2–3. C
OMPAQ I
PAQ D
ESKTOPS
, R
EAR
V
IEWS
............................................................................... 2-5
F
IGURE
2–4. C
OMPAQ I
PAQ 1.0/1.2 D
ESKTOP
C
HASSIS
L
AYOUT
.............................................................. 2-6
F
IGURE
2–5. C
OMPAQ I
PAQ 2.0 C
HASSIS
L
AYOUT
.................................................................................... 2-7
F
IGURE
2–6. C
OMPAQ I
PAQ 1.0/1.2 S
YSTEM
B
OARD
L
AYOUTS
................................................................ 2-8
F
IGURE
2–7. C
OMPAQ I
PAQ 2.0 S
YSTEM
B
OARD
L
AYOUT
........................................................................ 2-9
F
IGURE
2–8. C
OMPAQ I
PAQ 1.0/1.2 A
RCHITECTURE
, B
LOCK DIAGRAM
................................................... 2-11
F
IGURE
2–9. C
OMPAQ I
PAQ 2.0 A
RCHITECTURE
, B
LOCK DIAGRAM
......................................................... 2-13
F
IGURE
2–10. P
ROCESSOR
A
SSEMBLY AND
M
OUNTING
........................................................................... 2-15
F
IGURE
3–1. P
ROCESSOR
/M
EMORY
S
UBSYSTEM
A
RCHITECTURE
.............................................................. 3-1
F
IGURE
3–2. C
ELERON
P
ROCESSOR
I
NTERNAL
A
RCHITECTURE
................................................................. 3-2
F
IGURE
3–3. P
ENTIUM
III P
ROCESSOR
I
NTERNAL
A
RCHITECTURE
............................................................. 3-3
F
IGURE
3–4. S
YSTEM
M
EMORY
M
AP
......................................................................................................... 3-7
F
IGURE
4-1. PCI B
US
D
EVICES AND
F
UNCTIONS
......................................................................................... 4-2
F
IGURE
4-2. C
ONFIGURATION
C
YCLE
......................................................................................................... 4-4
F
IGURE
4-3. PCI C
ONFIGURATION
S
PACE
M
APPING
................................................................................... 4-5
F
IGURE
4-4. M
ASKABLE
I
NTERRUPT
P
ROCESSING
, B
LOCK
D
IAGRAM
........................................................ 4-7
F
IGURE
4-5. C
ONFIGURATION
M
EMORY
M
AP
........................................................................................... 4-11
F
IGURE
5-1. 40-P
IN
P
RIMARY
IDE C
ONNECTOR
(
ON SYSTEM BOARD
). ...................................................... 5-3
F
IGURE
5-2. 68-P
IN
M
ULTIBAY
C
ONNECTOR
(
ON
M
ULTIBAY BOARD
)........................................................ 5-4
F
IGURE
5-3. S
ERIAL
I
NTERFACE
C
ONNECTOR
(M
ALE
DB-9
AS VIEWED FROM REAR OF CHASSIS
)............... 5-6
F
IGURE
5-4. S
ERIAL
I
NTERFACE
H
EADER
(
I
PAQ 1.2
LEGACY
-
FREE AND
2.0
SYSTEM BOARDS ONLY
) ........ 5-7
F
IGURE
5-5. P
ARALLEL
I
NTERFACE
C
ONNECTOR
(F
EMALE
DB-25
AS VIEWED FROM REAR OF CHASSIS
)..5-14
F
IGURE
5-6. 8042-T
O
-K
EYBOARD
T
RANSMISSION OF
C
ODE
ED
H
, T
IMING
D
IAGRAM
.............................. 5-15
F
IGURE
5-7. K
EYBOARD OR
P
OINTING
D
EVICE
I
NTERFACE
C
ONNECTOR
.................................................. 5-21
F
IGURE
5-8. USB I/F, B
LOCK
D
IAGRAM
................................................................................................... 5-22
F
IGURE
5-9. USB P
ACKET
F
ORMATS
........................................................................................................ 5-23
F
IGURE
5-10. U
NIVERSAL
S
ERIAL
B
US
C
ONNECTOR
................................................................................. 5-25
F
IGURE
5-11. A
UDIO
S
UBSYSTEM
F
UNCTIONAL
B
LOCK
D
IAGRAM
........................................................... 5-27
F
IGURE
5-12. AC’97 L
INK
B
US
P
ROTOCOL
.............................................................................................. 5-28
F
IGURE
5-13. AD1881
OR
AD1885 A
UDIO
C
ODEC
F
UNCTIONAL
B
LOCK
D
IAGRAM
................................. 5-29
F
IGURE
5-14. N
ETWORK
I
NTERFACE
C
ONTROLLER
B
LOCK
D
IAGRAM
...................................................... 5-32
F
IGURE
5-15. E
THERNET
TPE C
ONNECTOR
(RJ-45,
VIEWED FROM CARD EDGE
)...................................... 5-36
F
IGURE
6-1. G
RAPHICS
S
UBSYSTEM
, B
LOCK DIAGRAM
.............................................................................. 6-2
F
IGURE
6-2. GMCH I
NTEGRATED
G
RAPHICS
S
UBSYSTEM
......................................................................... 6-3
F
IGURE
7–1. P
OWER
D
ISTRIBUTION AND
C
ONTROL
, B
LOCK
D
IAGRAM
....................................................... 7-1
F
IGURE
7–2.
I
PAQ 1.0/1.2 P
OWER
C
ABLE
D
IAGRAM
................................................................................. 7-4
F
IGURE
7–3.
I
PAQ 2.0 P
OWER
C
ABLE
D
IAGRAM
....................................................................................... 7-5
F
IGURE
7–4.
I
PAQ 1.0/1.2 S
IGNAL
D
ISTRIBUTION
D
IAGRAM
..................................................................... 7-7
F
IGURE
7–5.
I
PAQ 2.0 S
IGNAL
D
ISTRIBUTION
D
IAGRAM
........................................................................... 7-8
F
IGURE
7–6. S
YSTEM
B
OARD
H
EADER
P
INOUTS
........................................................................................ 7-9
F
IGURE
B–1. ASCII C
HARACTER
S
ET
........................................................................................................B-1