I
External Master Clear sequence for
16-bit
normal-speed asynchronous channel:
1.
0012
jk
Clear
output
channel to insure
CRAY-l
activity
on
the
channel
pair
has stopped.
2.
0012jk
3.
0011jk
4.
0010
j k
5.
tJ012jk
6.
Delay 1
7.
0011jk
8.
Delay 2
Clear
input
channel to insure external
activity
on
the
channel
pair
has
stopped.
Set the
input
channel
limit
to
an
arbitrary
value.
Set the
input
channel
current
address equal to the
same
value. This
initiates
the Master Clear
signal.
Clear the
input
channel. This stops the input channel
activity
just
initiated.
Device dependent -
this
determines the duration
of
the
Master
Clear
signal.
Set the
input
channel
limit.
This value
may
be
the
same
value as used in steps 3
and
4. This turns
off
the Master
Clear
signal.
Device dependent -
this
allows time
for
initialization
activities
in the attached device to complete.
Sequence for high-speed channels
For
the high-speed synchronous channel (SH/SI), delay 1 should
be
a
minimum
of
1 clock period
and
delay 2 a
minimum
of
20
clock periods.
External Master
Clear sequence
for
high-speed synchronous
and
asynchronous
(DN/DO)
channels:
1.
0012jk
2.
0012
j k
3.
0011jk
2240004
Clear
output
channel
interrupt
to assure
that
CRAY-l
activity
on
the channel
pair
has
stopped.
Clear
input
channel
interrupt
to assure
that
external
activity
on
the channel
pair
has
stopped.
Set the
output
channel
limit
to
an
arbitrary
value.
6-18
E
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