Cray CRAY-1 - Page 191

I
4.
0010 jk
5.
0012 j k
6.
Delay 1
7.
0011jk
8.
Delay 2
9.
MEMORY ACCESS
Set the output channel current address equal to the same
value. This initiates the Master Clear signal.
Clear the output channel. This stops the output channel
activity just initiated.
Device dependent - this determines the duration of the
Master
Clear signal.
Set the output channel limit. This value may be the same
value as used in steps 3 and 4. This turns off the Master
Clear signal.
Device dependent - this allows time for initialization
activities in the attached device to complete.
Read disk subsystem status (high-speed synchronous channel
only). A subsystem
status should be taken and discarded
to
remove any false status left by the Master Clear
sequence.
Each of the four channel groups is assigned a time slot (figure 6-2),
which is scanned once every four clock periods for a memory request. The
lowest-numbered channel in the group has the highest priority. A memory
request, whether accepted or rejected, causes the requesting channel to
miss the next time
slot. Therefore, any given channel can request a
memory reference only every eight clock periods. However, another channel
in the
same group as a channel that has just made a memory request can
cause a memory request four clock periods later. During the next three
clock periods, the scanner will allow requests
from the other three
channel groups. Therefore,
it is possible to have an I/O memory request
every clock period.
2240004
6-19
E