Cray CRAY-1 - Page 192

INPUT ASSEMBLY REG.
6% T ~TI~ {., .. C_H_ ... , __ 2_t7n
12 CHANNELS ........ 1 __ .--.
--1 ... ___ 30 ... 1
OUTPUT DISASSEMBLY REG.
16 BITS,. L_C_H ___ 3_
h
5
DATA OUT { - =-4 T
12 CHANNELS ~:::::::3:1:1
INPUT
READY
INPUT
RESUME
OUTPUT
READY
INPUT
READY
INPUT
RESUME
OUTPUT
READY
CHANNEL CONTROL
INPUT ADDRESS REG.
Ak :=::::t CH 2 ~6
ADV. ADDR. ~i'" ---~
I
,
OUTPUT ADDRESS REG.
Ak ~CH 3~5 7
ADV.
ADDR.~""'i"'· ---_
.'-- ..........
I/O DATA
FAN IN
rio DATA
FAN OUT
I/O ADDR
FAN IN
MEMORY
DATA MERGE
MEMORY
DATA DISTR.
NO SCALAR REF.
NO BLOCK MODE
NO EXCH. SEQ.
NO FE TCH
MEMORY
MEMORY
NO MEMORY CONFLICT
MEMORY
REQUEST ACCESS CONTR.
REFERENCE
GO I/O
MEMORY
ADDR. REG.
REQ.
RESP.
GO I/O
MEMORY
Figure 6-2. Channel I/O control
2240004
6-20
E