60 Piranha 2 User’s Manual
03-032-00493-14 Teledyne DALSA
image data bit allocations, refer to the official Camera Link specification on the
vfm.dalsa.com web site.
Camera Control Signals
Four LVDS pairs are reserved for general-purpose camera control. They are defined as
camera inputs and frame grabber outputs. Camera manufacturers can define these signals
to meet their needs for a particular product. The signals are:
• Cam era Control 1 (CC1)
• Cam era Control 2 (CC2)
• Cam era Control 3 (CC3)
• Cam era Control 4 (CC4)
Communication
Two LVDS pairs have been allocated for asynchronous serial communication to and from
the camera and frame grabber. Cameras and frame grabbers should support at least 9600
baud. These signals are
• SerTFG—Differential pair with serial communications to the frame grabber.
• SerTC—Differential pair with serial communications to the camera.
The serial interface will have the following characteristics: one start bit, one stop bit, no
parity, and no handshaking. It is recommended that frame grabber manufacturers supply
both a user interface and a software application programming interface (API) for using
the asynchronous serial communication port. The user interface will consist of a terminal
program with minimal capabilities of sending and receiving a character string and
sending a file of bytes. The software API will provide functions to enumerate boards and
send or receive a character string. See Appendix B in the Official Camera Link
specification on the vfm.dalsa.com web site.
Power
Power will not be provided on the Camera Link connector. The camera will receive
power through a separate cable. Camera manufacturers define their own power
connector, current, and voltage requirements.
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