Denon AVR-4520

207
Sil1292CNUC (NETWORK/DSP : U0802)
Sil1292CNUC Block diagram
SiI1292
(Top View)
1
11
21
31
RSVDL1
RSVDNC
HPD_IN
VDD33
2
12
22
32
VDD12
VREG33_OUT
TX2+
RXC-
3
13
23
33
RSVDL2
PS_CTRL#
TX2-
RXC+
4
14
24
34
RESET#
HDMI_DET
TX1+
RX0-
5
15
25
35
PWR5V_DET
GPIO1/CI2CA
TX1-
RX0+
6
16
26
36
INT#
GPIO0
TX0+
RX1-
7
17
27
37
DSDA
CSDA
TX0-
RX1+
8
18
28
38
DSCL
CSCL
TXC+
RX2-
9
19
29
39
CBUS/HPD
CEC_A
TXC-
RX2+
10
20
30
40
VDD5_IN
VDD12
AVDD12
VDD33
The ePad must be
grounded
RX2+
RX2-
RX1+
RX1-
RX0+
RX0-
RXC+
RXC-
MHL/HDMI Receiver Core
MHL Transcode
Engine
HDMI
Transmitter
Core
TXC-
TXC+
TX1-
TX1+
TX2-
TX2+
Registers, Configuration,
Control, and Power
Management Logic
CBUS Control
(DDC/HDCP/MSC)
CSOL
CSDA
RESET#
Local
I
2
C
CBUS Decode
CBUS/HPD
HPD_IN
CEC_A
DSCL
DSDA
HDMI Switch ModeINT
INT#
HDMI_DET
RX0+/- are used as the input data pair in MHL mode
and channel 0 input pair in HDMI mode
PS_CTRL#
PWR5V_DET
GPIO0
GPIO1/CI2CA
3.3 V Reg1.8 V Reg
VDD5_IN
VREG33_OUT
TX0-
TX0+