GE 750 - Page 486

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750/760 Feeder Management Relay GE Power Management
A.1 FIGURES AND TABLES APPENDIX A
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12–10: NEUTRAL DIRECTIONAL LOGIC DIAGRAM................................................................................. 12-22
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12–11: GROUND TIME OVERCURRENT LOGIC DIAGRAM .................................................................... 12-24
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12–12: GROUND INSTANTANEOUS OVERCURRENT LOGIC DIAGRAM .............................................. 12-26
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12–13: GROUND DIRECTIONAL LOGIC DIAGRAM ................................................................................. 12-29
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12–14: SENSITIVE GROUND TIME OVERCURRENT LOGIC DIAGRAM ................................................ 12-31
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12–15: SENSITIVE GROUND INSTANTANEOUS OVERCURRENT LOGIC DIAGRAM .......................... 12-33
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12–16: SENSITIVE GROUND DIRECTIONAL CURRENT......................................................................... 12-36
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12–17: SAMPLE APPLICATION ................................................................................................................. 12-38
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12–18: RESTRICTED EARTH FAULT LOGIC DIAGRAM.......................................................................... 12-40
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12–19: NEGATIVE SEQUENCE TIME OVERCURRENT LOGIC DIAGRAM............................................. 12-42
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12–20: NEGATIVE SEQUENCE INSTANTANEOUS OVERCURRENT LOGIC DIAGRAM....................... 12-44
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12–21: NEGATIVE SEQUENCE DIRECTIONAL LOGIC DIAGRAM.......................................................... 12-46
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12–22: NEGATIVE SEQUENCE VOLTAGE LOGIC DIAGRAM ................................................................. 12-48
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12–23: INVERSE TIME UNDERVOLTAGE CURVES ................................................................................ 12-50
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12–24: BUS UNDERVOLTAGE 1 / 2 LOGIC DIAGRAM ............................................................................ 12-51
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12–25: LINE UNDERVOLTAGE 3 / 4 LOGIC DIAGRAM............................................................................ 12-53
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12–26: OVERVOLTAGE 1 / 2 LOGIC DIAGRAM ....................................................................................... 12-55
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12–27: NEUTRAL DISPLACEMENT SCHEME LOGIC DIAGRAM ............................................................ 12-57
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12–28: UNDERFREQUENCY 1 / 2 LOGIC DIAGRAM ............................................................................... 12-59
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12–29: FREQUENCY DECAY LOGIC DIAGRAM....................................................................................... 12-61
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12–30: BREAKER FAILURE LOGIC DIAGRAM ......................................................................................... 12-63
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13–1: PHASE CURRENT LOGIC DIAGRAM................................................................................................ 13-2
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13–2: NEUTRAL CURRENT LOGIC DIAGRAM ........................................................................................... 13-3
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13–3: CAPACITOR BANK SWITCHING ....................................................................................................... 13-4
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13–4: POWER FACTOR LOGIC DIAGRAM ................................................................................................. 13-6
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13–5: THERMAL DEMAND CHARACTERISTIC (FOR 15 MIN. RESPONSE)............................................. 13-9
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13–6: CURRENT DEMAND LOGIC DIAGRAM .......................................................................................... 13-11
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13–7: REAL POWER DEMAND LOGIC DIAGRAM.................................................................................... 13-13
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13–8: REACTIVE POWER DEMAND LOGIC DIAGRAM ........................................................................... 13-15
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13–9: APPARENT POWER DEMAND LOGIC DIAGRAM.......................................................................... 13-17
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13–10: ANALOG INPUT THRESHOLD LOGIC DIAGRAM......................................................................... 13-21
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13–11: ANALOG INPUT RATE OF CHANGE MEASUREMENT................................................................ 13-22
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13–12: ANALOG INPUT RATE OF CHANGE LOGIC DIAGRAM............................................................... 13-23
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13–13: ANALOG OUTPUTS CHARACTERISTICS CHANNEL .................................................................. 13-24
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13–14: OVERFREQUENCY LOGIC DIAGRAM.......................................................................................... 13-28
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13–15: TRIP COUNTER LOGIC DIAGRAM................................................................................................ 13-30
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13–16: ARCING CURRENT MEASUREMENT........................................................................................... 13-31
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13–17: ARCING CURRENT LOGIC DIAGRAM.......................................................................................... 13-32
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13–18: BREAKER OPERATION LOGIC DIAGRAM ................................................................................... 13-34
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13–19: COIL MONITOR SCHEME LOGIC DIAGRAM................................................................................ 13-36
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13–20: VT FAILURE LOGIC DIAGRAM...................................................................................................... 13-38
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13–21: PULSE OUTPUT SCHEME LOGIC DIAGRAM............................................................................... 13-40
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14–1: SETPOINT CONTROL (1 OF 3).......................................................................................................... 14-3
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14–2: SETPOINT CONTROL (2 OF 3).......................................................................................................... 14-4
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14–3: SETPOINT CONTROL (3 OF 3).......................................................................................................... 14-5
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14–4: SYNCHROCHECK LOGIC DIAGRAM................................................................................................ 14-8
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14–5: MANUAL CLOSE BLOCKING LOGIC DIAGRAM............................................................................. 14-10
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14–6: COLD LOAD PICKUP ....................................................................................................................... 14-11
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14–7: COLD LOAD PICKUP LOGIC DIAGRAM ......................................................................................... 14-13
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14–8: UNDERVOLTAGE RESTORATION LOGIC DIAGRAM.................................................................... 14-15
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14–9: UNDERFREQUENCY RESTORATION LOGIC DIAGRAM .............................................................. 14-17
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14–10: TRANSFER SCHEME ONE LINE DIAGRAM ................................................................................. 14-23
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14–11: TRANSFER SCHEME INCOMER NO. 1 DC SCHEMATIC............................................................ 14-24
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14–12: TRANSFER SCHEME INCOMER NO. 2 DC SCHEMATIC............................................................ 14-25
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14–13: TRANSFER SCHEME BUS TIE BREAKER DC SCHEMATIC ....................................................... 14-26
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14–14: TRANSFER SCHEME INCOMER NO. 1 LOGIC DIAGRAM .......................................................... 14-27
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14–15: TRANSFER SCHEME INCOMER NO. 2 LOGIC DIAGRAM .......................................................... 14-28
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14–16: TRANSFER SCHEME BUS TIE BREAKER LOGIC DIAGRAM...................................................... 14-29
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14–17: AUTORECLOSE RATE SUPERVISION LOGIC DIAGRAM ........................................................... 14-34