Holtek BS66F340 - Page 165

Rev. 1.60 164 August 20, 2019 Rev. 1.60 165 August 20, 2019
BS66F340/BS66F350/BS66F360/BS66F370
Touch A/D Flash MCU with LED Driver
BS66F340/BS66F350/BS66F360/BS66F370
Touch A/D Flash MCU with LED Driver
Bit 4 Unimplemented, read as "0"
Bit 3~2 SIMDEB1~SIMDEB0: I
2
C Debounce Time Selection
00: No debounce
01: 2 system clock debounce
1x: 4 system clock debounce
Bit 1 SIMEN: SIM Enable Control
0: Disable
1: Enable
The bit is the overall on/off control for the SIM interface. When the SIMEN bit is
cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and
SCL lines will lose their SPI or I
2
C function and the SIM operating current will be
reduced to a minimum value. When the bit is high the SIM interface is enabled. The
SIM conguration option must have rst enabled the SIM interface for this bit to be
effective.If the SIM is congured to operate as an SPI interface via the SIM2~SIM0
bits, the contents of the SPI control registers will remain at the previous settings when
the SIMEN bit changes from low to high and should therefore be rst initialised by
the application program. If the SIM is congured to operate as an I
2
C interface via the
SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I
2
C
control bits such as HTX and TXAK will remain at the previous settings and should
therefore be first initialised by the application program while the relevant I
2
C flags
such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states.
Bit 0 SIMICF: SIM SPI slave mode Incomplete Transfer Flag
Described elsewhere.
• SIMC1 Register
Bit 7 6 5 4 3 2 1 0
Name HCF HAAS HBB HTX TXAK SRW IAMWU RXAK
R/W R R R R/W R/W R/W R/W R
POR 1 0 0 0 0 0 0 1
Bit 7 HCF: I
2
C Bus data transfer completion ag
0: Data is being transferred
1: Completion of an 8-bit data transfer
The HCF flag is the data transfer flag. This flag will be zero when data is being
transferred. Upon completion of an 8-bit data transfer the flag will go high and an
interrupt will be generated.
Bit 6 HAAS: I
2
C Bus data transfer completion ag
0: Not address match
1: Address match
The HAAS ag is the address match ag. This ag is used to determine if the slave
device address is the same as the master transmit address. If the addresses match then
this bit will be high, if there is no match then the ag will be low.
Bit 5 HBB: I
2
C Bus busy ag
0: I
2
C Bus is not busy
1: I
2
C Bus is busy
The HBB ag is the I
2
C busy ag. This ag will be "1" when the I
2
C bus is busy which
will occur when a START signal is detected. The ag will be set to "0" when the bus is
free which will occur when a STOP signal is detected.
Bit 4 HTX: I
2
C slave device transmitter/receiver selection
0: Slave device is the receiver
1: Slave device is the transmitter
Bit 3 TXAK: I
2
C bus transmit acknowledge ag
0: Slave send acknowledge ag
1: Slave does not send acknowledge ag
The TXAK bit is the transmit acknowledge ag. After the slave device receipt of 8-bits
of data, this bit will be transmitted to the bus on the 9
th
clock from the slave device.
The slave device must always set TXAK bit to "0" before further data is received.