Infineon TRAVEO T2G family CYT4D Series - 3.5 Setting the LPECO; 3.5.1 Use case

Application Note 23 of 80 002-26071 Rev. *B
2021-09-07
Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuration of the clock resources
3.5 Setting the LPECO
The LPCEO is disabled by default. The LPECO cannot be used unless it is enabled. Figure 11 shows how to
configure registers for enabling the LPECO. To disable the LPECO, write ‘0’ to the LPECO_EN bit of the
BACKUP_LPECO_CTL register.
Start
End(Success)
LPECO_STATUS is ready?
Enable LPECO
Yes
No
Configure value to BACKUP_LPECO_CTL
Specifies the load capacitance of the chosen crystal, the
crystal frequency range, and the oscillation amplitude
selection
(1)
(3)
Wait until LPECO is available
(2)
Figure 11 LPECO configuration
3.5.1 Use case
• Oscillator to use: Crystal unit
• Fundamental frequency: 8 MHz
Note: These values are decided in consultation with the crystal unit vendor.
Table 5 lists the parameters and Table 6 lists the functions of the configuration part of in the SDL for LPECO
settings.
Table 5 List of LPECO settings parameters
Parameters
Description
Value
WAIT_FOR_STABILIZATION
Waiting for stabilization
10000ul
CLK_FREQ_LPECO
Source clock frequency
8000000ul
CY_SYSCLK_BAK_LPECO_LCAP_
5TO10PF
Backup domain LPECO load is in the range of
5 pF to 10 pF.
0ul
CY_SYSCLK_BAK_LPECO_FREQ_
6TO8MHZ
Backup domain LPECO frequency is in the
range of 6 MHz to 8 MHz.
1ul
CY_SYSCLK_BAK_LPECO_AMP_
MAX_1P35V
Backup domain LPECO maximum oscillation
amplitude is 1.35 V.
0ul