Infineon TRAVEO T2G family CYT4D Series - Page 45

Application Note 45 of 80 002-26071 Rev. *B
2021-09-07
Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuration of the FLL and PLL
Code Listing 36 Cy_SysClk_PllManualConfigure() function
}
if((config->referenceDiv < MIN_REF_DIV) || (MAX_REF_DIV < config->referenceDiv))
{
return(CY_SYSCLK_BAD_PARAM);
}
if((config->feedbackDiv < (config->lfMode ? MIN_FB_DIV_LF : MIN_FB_DIV_NORM)) ||
((config->lfMode ? MAX_FB_DIV_LF : MAX_FB_DIV_NORM) < config->feedbackDiv))
{
return(CY_SYSCLK_BAD_PARAM);
}
un_CLK_PLL_CONFIG_t tempClkPLLConfigReg;
tempClkPLLConfigReg.u32Register = SRSS->unCLK_PLL_CONFIG[pllNo].u32Register;
if (tempClkPLLConfigReg.stcField.u1ENABLE != 0ul) /* 1 = enabled */
{
return(CY_SYSCLK_INVALID_STATE);
}
/* no errors */
/* If output mode is bypass (input routed directly to output), then done.
The output frequency equals the input frequency regardless of the frequency parameters. */
if (config->outputMode != CY_SYSCLK_FLLPLL_OUTPUT_INPUT)
{
tempClkPLLConfigReg.stcField.u7FEEDBACK_DIV = (uint32_t)config->feedbackDiv;
tempClkPLLConfigReg.stcField.u5REFERENCE_DIV = (uint32_t)config->referenceDiv;
tempClkPLLConfigReg.stcField.u5OUTPUT_DIV = (uint32_t)config->outputDiv;
tempClkPLLConfigReg.stcField.u1PLL_LF_MODE = (uint32_t)config->lfMode;
}
tempClkPLLConfigReg.stcField.u2BYPASS_SEL = (uint32_t)config->outputMode;
SRSS->unCLK_PLL_CONFIG[pllNo].u32Register = tempClkPLLConfigReg.u32Register;
return (CY_SYSCLK_SUCCESS);
}
Code Listing 37 Cy_SysClk_GetPllNo() function
__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_GetPllNo(uint32_t pathNo, uint32_t* pllNo)
{
/* check for error */
if ((pathNo <= SRSS_NUM_PLL400M) || (pathNo > (SRSS_NUM_PLL400M + SRSS_NUM_PLL)))
{
/* invalid clock path number */
return(CY_SYSCLK_BAD_PARAM);
}
*pllNo = pathNo - (uint32_t)(SRSS_NUM_PLL400M + 1u);
return(CY_SYSCLK_SUCCESS);
}
Code Listing 38 Cy_SysClk_PllCalucDividers() function
__STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_PllCalucDividers(uint32_t inFreq,
uint32_t targetOutFreq,
const cy_stc_pll_limitation_t* lim,
uint32_t fracBitNum,
uint32_t* feedBackDiv,
uint32_t* refDiv,
uint32_t* outputDiv,
uint32_t* feedBackFracDiv)
{
uint64_t errorMin = 0xFFFFFFFFFFFFFFFFull;
if(feedBackDiv == NULL)
{
return (CY_SYSCLK_BAD_PARAM);
}
if((feedBackFracDiv == NULL) && (fracBitNum != 0ul))
{
return (CY_SYSCLK_BAD_PARAM);
}
if(refDiv == NULL)
(9) PLL200 configuration