Infineon TRAVEO T2G family CYT4D Series - Page 44

Application Note 44 of 80 002-26071 Rev. *B
2021-09-07
Clock configuration setup in TRAVEO™ T2G family CYT4D series MCUs
Configuration of the FLL and PLL
Code Listing 34 AllClockConfiguration() function
static void AllClockConfiguration(void)
{
:
/***** PLL200M#0(PATH3) source setting ******/
{
:
status = Cy_SysClk_PllConfigure(PLL_200M_0_PATH_NO , &g_pll200_0_Config);
CY_ASSERT(status == CY_SYSCLK_SUCCESS);
status = Cy_SysClk_PllEnable(PLL_200M_0_PATH_NO, WAIT_FOR_STABILIZATION);
CY_ASSERT(status == CY_SYSCLK_SUCCESS);
:
}
return;
}
Code Listing 35 Cy_SysClk_PllConfigure() function
cy_en_sysclk_status_t Cy_SysClk_PllConfigure(uint32_t clkPath, const cy_stc_pll_config_t *config)
{
/* check for error */
uint32_t pllNo;
cy_en_sysclk_status_t status = Cy_SysClk_GetPllNo(clkPath, &pllNo);
if(status != CY_SYSCLK_SUCCESS)
{
return(status);
}
if (SRSS->unCLK_PLL_CONFIG[pllNo].stcField.u1ENABLE != 0ul) /* 1 = enabled */
{
return (CY_SYSCLK_INVALID_STATE);
}
/* invalid output frequency */
cy_stc_pll_manual_config_t manualConfig = {0ul};
const cy_stc_pll_limitation_t* pllLim = (config->lfMode) ? &g_limPllLF : &g_limPllNORM;
status = Cy_SysClk_PllCalucDividers(config->inputFreq,
config->outputFreq,
pllLim,
0ul, // Frac bit num
&manualConfig.feedbackDiv,
&manualConfig.referenceDiv,
&manualConfig.outputDiv,
NULL
);
if(status != CY_SYSCLK_SUCCESS)
{
return(status);
}
/* configure PLL based on calculated values */
manualConfig.lfMode = config->lfMode;
manualConfig.outputMode = config->outputMode;
status = Cy_SysClk_PllManualConfigure(clkPath, &manualConfig);
return (status);
}
Code Listing 36 Cy_SysClk_PllManualConfigure() function
cy_en_sysclk_status_t Cy_SysClk_PllManualConfigure(uint32_t clkPath, const cy_stc_pll_manual_config_t *config)
{
/* check for error */
uint32_t pllNo;
cy_en_sysclk_status_t status = Cy_SysClk_GetPllNo(clkPath, &pllNo);
if(status != CY_SYSCLK_SUCCESS)
{
return(status);
}
/* valid divider bitfield values */
if((config->outputDiv < MIN_OUTPUT_DIV) || (MAX_OUTPUT_DIV < config->outputDiv))
{
return(CY_SYSCLK_BAD_PARAM);
PLL200 enable. See Code Listing 39.
PLL200 configuration. See Code Listing 35 .
PLL200 calculation for dividers settings. See Code Listing 38.
PLL200 manual configuration. See Code Listing 36.
(8) Check if PLL200 is already enabled.