Introduction to Digital Power Conversion
XMC4000/1000 Family
Modulation
Application Guide 57 V1.0, 2015-01
PWM and ACC Sampling Points, Controlled by Dual-Channel Compare Events
The Compare Register CR1 value defines the Duty-Cycle.
CR2 defines the ACC sampling points and is a ‘follower’ to CR1 by its value =
1
/
2
CR1 value.
The software, including the H(z) frequency compensation, controls any successive PWM cycles by an
updated ‘Next CR1/CR2’ setup.
Steady State Frequency Response in ACC Loop
The ACC loop is described by the ‘Sense-Loop-Drive’ (shown in blue in the previouis figure). The loop
is repeated each or every n
th
cycle (which is better with some accumulated intermediate samplings).
The transfer function frequency response will be stabilized by the H(z) transfer compensating
software. There are DSP operations on discrete time variables, maintained by the Interrupt Service
Request (ISR) provider, stimulated by the VADC result stream that is synchronized and triggered by
the PWM.
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