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Intel Agilex 7 FPGA I-Series User Manual

Intel Agilex 7 FPGA I-Series
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6. Custom Projects for the Development Kit
6.1. Add SmartVID Settings in the Intel Quartus Prime QSF File
Intel Agilex 7 silicon assembled on this development kit enables SmartVID feature by
default. In order to avoid the Intel Quartus Prime from generating an error due to
incomplete SmartVID settings, you must put constraints outlined below into Intel
Quartus Prime project QSF file. These constraints are designed for LTC3888 PMIC.
Open your Intel Quartus Prime project QSF file, copy and paste constraint scripts into
the file. Ensure that there are no other similar settings with different values.
set_global_assignment -name PWRMGT_SLAVE_DEVICE_TYPE LTC3888
set_global_assignment -name PWRMGT_SLAVE_DEVICE0_ADDRESS 62
set_global_assignment -name PWRMGT_SLAVE_DEVICE1_ADDRESS 00
set_global_assignment -name PWRMGT_SLAVE_DEVICE2_ADDRESS 00
set_global_assignment -name ACTIVE_SERIAL_CLOCK AS_FREQ_100MHZ
set_global_assignment -name USE_PWRMGT_SCL SDM_IO0
set_global_assignment -name USE_PWRMGT_SDA SDM_IO12
set_global_assignment -name USE_CONF_DONE SDM_IO16
set_global_assignment -name VID_OPERATION_MODE "PMBUS MASTER"
set_global_assignment -name PWRMGT_VOLTAGE_OUTPUT_FORMAT "LINEAR FORMAT"
set_global_assignment -name PWRMGT_LINEAR_FORMAT_N "-12"
set_global_assignment -name PWRMGT_TRANSLATED_VOLTAGE_VALUE_UNIT VOLTS
6.2. Golden Top
You can use the Golden Top project as the starting point for your designs. It comes
loaded with constraints, pin locations, define I/O standard, direction and general
termination. DDR4 pin termination settings are not included. Refer DDR4 example
designs for details.
776646 | 2023.05.31
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Intel Agilex 7 FPGA I-Series Specifications

General IconGeneral
BrandIntel
ModelAgilex 7 FPGA I-Series
CategoryMicrocontrollers
LanguageEnglish

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