Intel Agilex User Guide

•
fp32_adder_inexact
•
fp32_adder_overflow
•
fp32_adder_underflow
The following are exception flags supported in extended format:
•
fp16_mult_top_invalid
•
fp16_mult_top_inexact
•
fp16_mult_top_infinite
•
fp16_mult_top_zero
•
fp16_mult_bot_invalid
•
fp16_mult_bot_inexact
•
fp16_mult_bot_infinite
•
fp16_mult_bot_zero
•
fp16_adder_invalid
•
fp16_adder_inexact
•
fp16_adder_infinite
•
fp16_adder_zero
•
fp32_adder_invalid
•
fp32_adder_inexact
•
fp32_adder_overflow
•
fp32_adder_underflow
Figure 35. Sum of Two FP16 Multiplication with Accumulation Mode
fp32_chainout[31:0]
accumulate
fp16_mult_top_a[15:0]
fp32_result[31:0]
Input
Register
Bank
Top
Multiplier
Adder
*Pipeline
Register
*Pipeline
Register
*Pipeline
Register
*Pipeline
Register
*Pipeline
Register
Output
Register
Bank
*This block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block.
fp16_mult_top_b[15:0]
fp16_mult_bot_a[15:0]
Bottom
Multiplier
fp16_mult_bot_b[15:0]
*Pipeline
Register
Register
Adder
fp16_mult_top_invalid
fp16_mult_top_underflow
fp16_mult_top_overflow
fp32_adder_invalid
fp32_adder_inexact
fp32_adder_overflow
fp32_adder_underflow
fp16_mult_top_inexact
fp16_mult_bot_invalid
fp16_mult_bot_underflow
fp16_mult_bot_overflow
fp16_mult_bot_inexact
fp16_adder_invalid
fp16_adder_inexact
fp16_adder_overflow
fp16_adder_underflow
fp16_mult_top_infinite(extended format)
fp16_mult_top_zero(extended format)
fp16_mult_bot_infinite(extended format)
fp16_mult_bot_zero(extended format)
fp16_adder_infinite(extended format)
fp16_adder_zero(extended format)
3. Intel Agilex Variable Precision DSP Blocks Operational Modes
UG-20213 | 2019.04.02
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Variable Precision DSP Blocks User Guide
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Intel Agilex Specifications

General

Brand	Intel
Model	Agilex
Category	Microcontrollers
Language	English