4.2.1.2. FP16 Operation Mode Supported Register Configurations
Table 32. Supported Register Configurations For Sum of Two FP16 Multiplication Mode
Latency Data Input
Register
Multiplier 1st
Pipeline
Register
Multiplier 2nd
Pipeline
Register
Adder Input
Register
Adder Pipeline
Register
Output
Register
fp16_mult_inp
ut_clken
mult_pipeline
_clken
mult_2nd_pip
eline_clken
adder_input_c
lken
adder_pl_clke
n
output_clken
0 Disable Disable Disable Disable Disable Disable
1 Enable Disable Disable Disable Disable Disable
1 Disable Disable Disable Disable Enable
2 Enable Disable Disable Disable Enable
3 Enable Disable Disable Enable Disable Enable
4 Enable Disable Disable Enable Enable Enable
≥5 Enable Disable, enable Enable Enable Enable Enable
Table 33. Supported Register Configurations For Sum of Two FP16 Multiplication with
FP32 Addition Mode
Latency Data Input Register Adder 1st
Pipeline
Register
Adder
2nd
Pipeline
Register
Multiplier
1st
Pipeline
Register
Multiplier
2nd
Pipeline
Register
Adder
Input
Register
Adder
Pipeline
Register
Output
Register
fp32_add
er_a_clke
n
fp16_mul
t_input_c
lken
fp32_add
er_a_chai
nin_pl_cl
ken
fp32_add
er_a_chai
nin_2nd_
pl_clken
mult_pipe
line_clke
n
mult_2nd
_pipeline
_clken
adder_inp
ut_clken
adder_pl_
clken
output_cl
ken
0 Disable Disable Disable Disable Disable Disable Disable Disable Disable
1 Enable Enable Disable Disable Disable Disable Disable Disable Disable
1 Disable Disable Disable Disable Disable Disable Disable Disable Enable
2 Enable Enable Disable Disable Disable Disable Disable Disable Enable
≥3 Enable Enable Disable,
enable
Disable,
enable
Disable Disable Enable Disable Enable
≥4 Enable Enable Disable,
enable
Disable,
enable
Disable Disable Enable Enable Enable
≥5 Enable Enable Disable,
enable
Disable,
enable
Disable,
enable
Enable Enable Enable Enable
4. Intel Agilex Variable Precision DSP Blocks Design Considerations
UG-20213 | 2019.04.02
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Variable Precision DSP Blocks User Guide
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