Intel altera Cyclone V SoC - Page 17

In the following table, up and down indicates the position of the switch with the
board orientation as shown in the Switch Locations and Default Settings for Power
Solution 2 figure.
Table 5. SW4 JTAG DIP Switch Settings
Switch Board Label Function Default Position
1 HPS • ON (up)—Do not include HPS in the JTAG chain.
• OFF (down)—Include HPS in the JTAG chain.
OFF
2 FPGA • ON (up)—Do not include the FPGA in the JTAG
chain.
• OFF (down)—Include the FPGA in the JTAG chain.
OFF
3 HSMC • ON (up)—Do not include the HSMC connector in
the JTAG chain.
• OFF (down)—Include the HSMC connector in the
JTAG chain.
ON
4 MAX • ON (up)—Do not include the MAX V system
controller in the JTAG chain.
• OFF (down)—Include the MAX V system controller
in the JTAG chain.
OFF
4. Set the DIP switch bank (SW6) to match the SW6 JTAG DIP Switch Settings table.
In the following table, up and down indicates the position of the switch with the
board orientation as shown in the Switch Locations and Default Settings for Power
Solution 2 figure.
Table 6. SW6 JTAG DIP Switch Settings
Switch Board Label Function Default Position
1 I2C_SDA_HPS • ON (down)—Include HPS in the JTAG chain.
• OFF (up)—Do not include HPS in the JTAG chain.
ON
2 I2C_SCL_HPS • ON (down)—Include HPS in the JTAG chain.
• OFF (up)—Do not include HPS in the JTAG chain.
ON
3 I2C_SCL • ON (down)—Include the FPGA in the JTAG chain.
• OFF (up)—Do not include the FPGA in the JTAG
chain.
ON
4 I2C_SDA • ON (down)—Include the FPGA in the JTAG chain.
• OFF (up)—Do not include the FPGA in the JTAG
chain.
ON
5. Set the following jumper blocks to match the Default Jumper Settings for Power
Solution 2 Board table and the Switch Locations and Default Settings for Power
Solution 2 Board figure.
3. Development Kit Setup
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V SoC Development Kit User Guide
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