EasyManua.ls Logo

Intel S5500BC

Intel S5500BC
119 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
Functional Architecture Intel
®
Server Board S5500BC TPS
Intel order number: E42249-003 Revision 1.0
22
Figure 14. ILM backplate and URS
3.2 Memory Sub-system
3.2.1 Integrated Memory Controller
The Intel
®
Xeon
®
processors 5500 series has an Integrated Memory Controller (IMC). The Intel
®
Server Board S5500BC memory interface supports up to three DDR3 channels. Each channel
consists of 64 data and 8 ECC bits. The IMC provides DDR3 channels and groups DIMMs on

Table of Contents

Other manuals for Intel S5500BC

Related product manuals