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ECP5 and ECP5-5G High-Speed I/O Interface
Figure 40. SDR Configuration Tab
Table 6 explains the various configurations options available for SDR modules.
Table 6. SDR Configuration Parameters
GUI Option Description Values Default
Interface Type Type of Interface (Transmit or
Receive)
Transmit, Receive Receive
I/O Standard for this Interface I/O Standard to be used for the
interface
All Valid IO_TYPES LVCMOS25
Bus Width for this Interface Bus size for the interface 1 – 256 16
Clock Frequency for this Interface Interface Speed 1 - 200 200
Bandwidth (Calculated) This is the calculated from the
Clock frequency entered
(Calculated) (calculated)
Interface Interface selected based on previ-
ous entries
Tra ns mit :
GOREG_TX.SCLK
Receive:
GIREG_RX.SCLK
(default)
GIREG_RX.SCLK
Clock Inversion Option to invert the clock Input to
the IO Register
DISABLED, ENABLED DISABLED
Data Path Delay
1
Data input can be optionally
delayed using the DELAY block
If Interface Type= Receive
then:
Bypass,
Static Default
Dynamic Default
Static User Defined
Dynamic User Defined
If Interface Type= Trans-
mit then:
Bypass,
Static User Defined
Dynamic User Defined
Bypass
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