Lattice Semiconductor ECP5 Technical Notes

48
ECP5 and ECP5-5G High-Speed I/O Interface
Gearing Ratio DDR register gearing ratio 2:1, 4:1 2:1
Alignment Clock to Data alignment Edge-to-Edge or Cen-
tered
Centered
Bus Width Bus width for each interface. 1 – 256 10
Organize Parallel Data Allows user to select how the data
bits of the parallel bus should be
arranged. You can choose to set it
By Lane where all the parallel data
bits from each lane are organized
together in the data output. If By
Time is chosen instead, a single bit
from each of the data lanes is put
together in the data output.
By Lane, By Time By Time
Enable ECLK Bridge
(required if bus is crossing sides)
This is required if the data bus is
wide and will be crossing sides.
Enabling this option will instantiate
the ECLK Bridge module in the
HDL
Enable, Disable Disable
Interface Shows list of all valid high speed
Interfaces for the given configura-
tion
Refer to the table below to
see interfaces available
for a given configuration.
Data Path Delay Data input can be optionally
delayed using the DELAY block.
Default Value is selected based on
Interface Type.
If Interface Type =
Receive:
Static Default,
Dynamic Default,
Static User Defined,
Dynamic User Defined
If interface type = Receive
MIPI
Static Default
Static User Defined
If Interface Type = 
Tra ns mit :
Bypass,
Static User Defined,
Dynamic User Defined
If Interface Type=
Receive:
Static Default
If Interface Type= Trans-
mit:
Bypass
Delay Value for User Defined When Data Path Delay of user
defined is selected, the user will
also need to set the number of
delay steps to be used
1– 127 1
Enable Dynamic Margin Control on
Clock Delay
Allows dynamic user control on
clock phase shift for Receiver edge
to edge aligned interfaces
Enable, Disable Disable
Generate PLL with this module When is option is enabled for
Transmit interfaces, the PLL used
to generate the clocks is included
in the generated module
Enable, Disable Disable
PLL Input Clock Frequency Frequency of the clock used as
PLL Input
10 MHz – 400 MHz
GUI Option Description Values Default Value

Lattice Semiconductor ECP5 Specifications

General

Brand	Lattice Semiconductor
Model	ECP5
Category	Recording Equipment
Language	English