Configuration
Code table
8
8.5
8.5−26
EDSVF9383V EN 4.0−03/2006
IMPORTANTPossible settingsCode
SelectionLenzeNameNo.
C0405 DIS: OUT −199.99 {0.01 %} 199.99 Analog output signal, function
block AIN2
l Read only
See System
Manual
(extension)
C0407
CFG: OFFSET 19503 FCODE−26/2 Selection list 1 Configuration of offset, function
block AIN2
l The offset is added to the
input signal at AIN2−IN
C0408
CFG: GAIN 19505 FCODE−27/2 Selection list 1 Configuration of gain, function
block AIN2
l The gain is multiplied by the
input signal at AIN2−IN
C0409 −199.99 {0.01 %} 199.99
Function block AIN2
l Display of the signals linked
in C0407 and C0408
1 DIS: OFFSET
2 DIS: GAIN
C0420
Encoder const 512 1 {1 inc/rev} 8192 Number of increments for
incremental encoder at X8 or X9
l Connect incremental
encoders with HTL−level on
X9 only
6.7−1
C0421
Enc voltage 5.00 5.00 {0.1 V} 8.00 Supply voltage for the
incremental encoder at X8
CAUTION! A wrong entry can
destroy the incremental
encoder!
C0425 DFIN const 3
0 256 inc/rev
Constant of the master
frequency input, function block
DFIN
l Output signal at the
connected encoder or at the
upstream controller in the
event of a master frequency
cascade/master frequency
bus
8.2−5
1 512 inc/rev
2 1024 inc/rev
3 2048 inc/rev
4 4096 inc/rev
5 8192 inc/rev
6 16384 inc/rev
C0426 DIS: OUT −36000 {1 rpm} 36000 Output signal of the master
frequency input, function block
DFIN
l Display only
C0427 DFIN function 0
Function of the master
frequency input, function block
DFIN
0 2−phase l Phase−displaced signal
sequence
1 A pulse/B dir l Control of direction of
rotation via track B
2 Pulse A or B l Control of speed and
direction of rotation via track
A or track B
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