LSIS XBF-AH04A - Page 273

XGB Analog edition manual
7.11 Configuration and Function of Internal Memory
An analog mix module has internal memory for data communication with XGB base unit.
7.11.1 Analog Data I/O Area
The table below presents the analog data I/O area.
Variable Type
Device assignment
Description
Read/
Write
Signal
direction
“S”or
“H”type
IEC type
_0y_ERR
BIT
U0y.00.0
%UX0.y.0
Module Error
Read AD08A → CPU
_0y_RDY
BIT
U0y.00.F
%UX0.y.15
Module Ready
_0y_CH0_ACT
BIT
U0y.01.0
%UX0.y.16
CH0 Active
Read AD08A → CPU
_0y_CH1_ACT
BIT
U0y.01.1
%UX0.y.17
CH1 Active
_0y_CH2_ACT
BIT
U0y.01.2
%UX0.y.18
CH2 Active
_0y_CH3_ACT
BIT
U0y.01.3
%UX0.y.19
CH3 Active
_0y_CH4_ACT
BIT
U0y.01.4
%UX0.y.20
CH4 Active
_0y_CH5_ACT
BIT
U0y.01.5
%UX0.y.21
CH5 Active
_0y_CH6_ACT
BIT
U0y.01.6
%UX0.y.22
CH6 Active
_0y_CH7_ACT
BIT
U0y.01.7
%UX0.y.23
CH7 Active
_0y_CH0_ERR
BIT
U0y.01.8
%UX0.y.24
CH0 error
Read AD08A → CPU
_0y_CH1_ERR
BIT
U0y.01.9
%UX0.y.25
CH1 error
_0y_CH2_ERR
BIT
U0y.01.A
%UX0.y.26
CH2 error
_0y_CH3_ERR
BIT
U0y.01.B
%UX0.y.27
CH3 error
_0y_CH4_ERR
BIT
U0y.01.C
%UX0.y.28
CH4 error
_0y_CH5_ERR
BIT
U0y.01.D
%UX0.y.29
CH5 error
_0y_CH6_ERR
BIT
U0y.01.E
%UX0.y.30
CH6 error
_0y_CH7_ERR
BIT
U0y.01.F
%UX0.y.31
CH7 error
_0y_CH0_DATA
WORD
U0y.02
%UW0.y.2
CH0 Output
Read AD08A → CPU
_0y_CH1_DATA
WORD
U0y.03
%UW0.y.3
CH1 Output
_0y_CH2_DATA
WORD
U0y.04
%UW0.y.4
CH2 Output
_0y_CH3_DATA
WORD
U0y.05
%UW0.y.5
CH3 Output
_0y_CH4_DATA
WORD
U0y.06
%UW0.y.6
CH4 Output
_0y_CH5_DATA
WORD
U0y.07
%UW0.y.7
CH5 Output
_0y_CH6_DATA WORD U0y.08 %UW0.y.8 CH6 Output
_0y_CH7_DATA
WORD
U0y.09
%UW0.y.9
CH7 Output
_0y_CH0_IDD
BIT
U0y.10.0
%UX0.y.160
CH0 Disconnection flag
Read AD08A → CPU
_0y_CH1_IDD
BIT
U0y.10.1
%UX0.y.161
CH1 Disconnection flag
_0y_CH2_IDD
BIT
U0y.10.2
%UX0.y.162
CH2 Disconnection flag
_0y_CH3_IDD
BIT
U0y.10.3
%UX0.y.163
CH3 Disconnection flag
_0y_CH4_IDD
BIT
U0y.10.4
%UX0.y.164
CH4 Disconnection flag
_0y_CH5_IDD
BIT
U0y.10.5
%UX0.y.165
CH5 Disconnection flag
_0y_CH6_IDD
BIT
U0y.10.6
%UX0.y.166
CH6 Disconnection flag
_0y_CH7_IDD BIT U0y.10.7 %UX0.y.167 CH7 Disconnection flag
_0y_ERR_CLR BIT U0y.11.0 %UX0.y.176 Error Clear Request
Read/
Write
AD08A ↔ CPU
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