5.3 MC68705R3/MC68705U3
AND
MC68705R5/MC68705U5 TIMER CIRCUITRY
The timer for the MC68705R3 and MC68705U3 microcomputers
is
shown
in
Figure
5-3
and the timer
for the MC68705R5 and MC68705U5 microcomputers
is
shown
in
Figure
5-4.
The timer for all four
devices contains
an
8-bit software programmable counter which
is
driven
by
a 7-bit prescaler with
one-of-eight selectable outputs. Various timer clock sources may
be
selected ahead
of
the prescaler
and counter. The timer selections
are
made via the timer control register
(TCR)
and/or
the mask op-
tion register
(MOR). The
TCR
also contains the interrupt control bits. Note that the MC68705R5 and
MC68705U5 offer a secure/non-secure mode option which
is
implemented through bit 3
of
the
mask option register (refer
to
SECTION 9
MASK
OPTIONS
AND
PROGRAMMING for further infor-
mation regarding the secure/ non-secure mode option).
The 8-bit counter may
be
loaded under program control and
is
decremented toward zero by the
counter input frequency
(fCIN) input (output
of
the prescaler selector). Once the 8-bit counter
has
decremented
to
zero, it sets the
TIR
(timer interrupt request) bit 7
(b7
of TCR)' The TIM (timer inter-
rupt
mask)
bit
(b6)
can
be
software set
to
inhibit the interrupt request, or software cleared
to
pass
the interrupt request to the processor. When the I bit
in
the condition code register
is
cleared, the
processor receives the timer interrupt. The MCU responds to this interrupt by saving the present
CPU
state
on
the stack, fetching the timer interrupt vector from locations
$FF8
and
$FF9,
and
executing the interrupt routine. The processor
is
sensitive
to
the level
of
the timer interrupt request
line; therefore if the interrupt
is
masked, the
TIR
bit may
be
cleared by software (e.g., BClR)
without generating
an
interrupt. The
TIR
bit must
be
cleared by the timer interrupt service routine
to
clear the timer interrupt request.
The timer interrupt and
INT2 share the
same
interrupt vector. The interrupt routine thus must check
the
two
request bits to determine the source of the interrupt.
The counter continues to count (decrement) by falling through to
$FF
from zero. Thus, the counter
can
be
read
at any time by the processor without disturbing the count. This allows a program to
determine the length
of
time since the occurrence
of
a timer interrupt
and
does not disturb the
counting process.
The clock input to the timer
can
be
from
an
external source (decrementing the counter occurs
on
a
positive transition of the external source) applied to the
TIMER input pin, or it can
be
the internal
phase
two
Signal.
The maximum frequency of a signal that
can
be
recognized by the TIMER or Il\li
pin logic
is
dependent
on
the parameter labeled
tWl,
tWH. The pin logic that recognizes the low (or
high) state
on
the pin
in
order to "re-arm" the internal logic. Therefore, the period can
be
calculated
as
follows (assumes 50/50 duty cycle for a given period):
tcyc x 2
+
250
ns
= period =
-f
1
req
The period
is
not simply
tWl
+ tWH. This computation
is
allowable, but it does reduce the maxi-
mum allowable frequency by defining
an
unnecessarily longer period
(250
nanoseconds twice).
When the phase
two
signal
is
used
as
the source, it
can
be
gated
by
an
input applied to the TIMER
pin allowing the user to easily perform pulse width measurements. The source
of
the clock input
is
selected
via
the
TCR
or the
MOR
as
described later.
5-5
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