A prescaler option
can
be
applied to the clock input that extends the timing interval up
to
a maxi-
mum
of
128
counts before decrementing the counter. This prescaling
TCR
or
MaR
option selects
one
of
eight outputs on the 7-bit binary divider; one output bypasses prescaling. To avoid trunca-
tion errors, the
prescaler
is
cleared when bit 3
(b3)
of
the
TCR
is
written to a logic one; however,
TCR
bit 3 always reads
as
a logic zero to ensure proper operation
with
read-modify-write instruc-
tions (bit set and clear for
example).
At
reset, the prescaler and counter
are
initialized to
an
all
ones condition; the timer interupt request
bit
(TCR,
b7)
is
cleared and the timer interrupt request mask (TCR,
b6)
is
set.
TCR
bits
bO,
b1,
b2,
b4,
and
b5
are
initialized by the corresponding mask option register (MaR) bits at reset. They are
then software
selectable after reset (if the TOPT bit
(b6)
in
the MORE
is
equal to zero).
Note that the timer
block diagrams
in
Figures 5-3 and 5-4 reflect
two
separate timer control con-
figurations:
a)
software controlled mode via the timer control register (TCR), and
b)
MaR
controlled
mode to emulate a mask
ROM
version
with
the mask option register.
In
the software controlled
mode, all
TCR
bits are read/write, except bit
b3
which
is
write-only (always reads
as
a logic zero).
In
the
MaR
controlled mode, for
all
four devices,
TCR
bit
b7
and
b6
are read/write
and
bits
b5, b4,
b2,
b1,
and
bO
have no effect on a write (always
read
as
logic ones). For the MC68705R3/ MC68705U3,
bit
b3
is
write-only (reads
as
logic zero), and for the MC68705R5/MC68705U5, bit
b3
has
no effect
on a write (reads
as
a logic
one~.
5.3.1 Software Controlled Mode
The TOPT (timer option) bit
(b6)
in
the mask option register
is
EPROM
programmed to a logic zero
to
select the software controlled mode, which
is
described first.
TCR
bits
b5,
b4,
b3,
b2, b1,
and
bO
give the program direct control
of
the prescaler and input select options.
The timer
prescaler input frequency (fPIN)
can
be
configured for three different operating modes
plus a disable mode, depending upon the value written to
TCR
control bits
b4
and
b5
(TIE and TIN).
When the
TIE
and TIN bits
are
programmed to zero the timer input
is
from the internal clock (phase
two) and
TIMER input pin
is
disabled. The internal clock mode
can
be
used
for periodic interrupt
generation
as
well
as
a reference for frequency and event measurement.
When
TIE=
1 and TIN =
0,
the internal clock and the TIMER input pin signals
are
ANDed to form the
timer input. This mode
can
be
used to measure external pulse widths. The external pulse simply
gates in the internal clock for the duration
of
the pulse. The accuracy
of
the count
in
this mode
is
plus or minus one count.
When
TIE= 0 and TIN =
1,
no prescaler input frequency
is
applied to the prescaler and the timer
is
disabled.
When
TIE
and TIN
are
both programmed
to
a one, the timer
is
from the external clock. The external
clock
can
be
used to count external events
as
well
as
provide
an
external frequency for generating
periodic interrupts.
Bits
bO,
b1,
and
b2
in
the
TCR
are program controlled to choose the appropriate prescaler output.
The
prescaling divides the prescaler input frequency by
1,
2,
4, etc.
in
binary multiplex to
128
pro-
ducing counter input frequency to the counter. The processor cannot write into or
read
from the
5-8
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