useful
in
selecting the kth element
in
an
n element table. With this two-byte instruction, k would
typically
be
in
X with the address
of
the beginning
of
the table
in
the instruction. As such, tables
may begin anywhere within the first
256
addressable locations and could extend
as
far
as
location
510
($1
FE
is
the last location at which the instruction may beginl.
10.2.7 Index, 16-Bit Offset
In
the indexed, 16-bit offset addressing mode, the effective address
is
the sum
of
the contents
of
the unsigned 8-bit index register and the
two
unsigned bytes following the opcode. This addressing
mode
can
be
used
in
a manner similar to indexed, 8-bit offset except that this three-byte instruction
allows tables
to
be
anywhere
in
memory. As
with
direct and extended, the Motorola determines the
shortest form
of
indexed addressing.
10.2.8 Bit Set/Clear
I
n the bit set/ clear addressing mode, the bit to
be
set or cleared
is
part
of
the opcode, and the byte
following the opcode specifies the direct addressing
of
the byte
in
which the specified bit
is
to
be
set
or cleared. Thus, any read/write bit
in
the first
256
locations
of
memory, including
I/O,
can
be
selectively set or cleared with a single two-byte instruction.
CAUTION
The corresponding DDRs for ports A,
B,
and C
are
write-only registers (registers at
$004,
$005,
and
$006).
A
read
operation on these registers
is
undefined since BSET and
BCLR
are
read-modify-write
in
function, they cannot
be
used to set or clear a single
DDR
bit
(all
"unaffected"
bits would
be
setl. It
is
recommended that
all
DDR
bits
in
a port must
be
written using a single-store instruction.
10.2.9 Bit Test and Branch
The bit test and branch addressing mode
is
a combination
of
direct addressing
and
relative address-
ing. The bit which
is
to
be
tested and condition (set or
clear)
is
included
in
the opcode, and the
address
of
the byte to
be
tested
is
in
the single byte immediately following the opcode byte. The
Signed
relative 8-bit offset
in
the third byte
is
added to the
PC
if the specified bit.is set or cleared
in
the specified memory location. This single three-byte instruction allows the program to branch
based on the condition
of
any readable bit
in
the first
256
locations
of
memory. The span of bran-
ching
is
from
-125
to +
130
from the opcode address. The state
of
the tested bit
is
also transferred
to
the carry bit
of
the condition code registers.
See
Caution under paragraph 10.2;8.
10.2.10 Inherent
In
the inherent addressing mode,
all
the information necessary to execute the instruction
is
con-
tained
in
the opcode. Operations specifying only the index register or accumulator,
as
well
as
con-
trol instruction with no other agruments, are included
in
this mode. These instructions are one byte
long.
10.3 INSTRUCTION SET
The MCU
has
a set
of
59
basic instructions, which when combined
with
the
10
addressing modes
produce
207
usable opcodes. They
can
be
divided into five types: register/memory, read-modify-
write, branch, bit manipulation, and
control. The following paragraphs briefly explain
each
type. All
the instructions within a given type are presented
in
individual tables.
10-3
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