Motorola MC6805R Series - Page 71

Control Register/ Memory
INH INH IMM DIR
EXT 1X2
IX1 IX
8 9
A B C
0
E
F
~
1(0)
1001
1010 1011 1100 1101 1110 1111
I Low
9
9
2
2 4
3 5
4 6
5 5
4 4
3
RTI SUB
SUB SUB
SUB SUB SUB
0
1 INI1
2
IMM 2 DIR 3
EXT 3 IX2 2
IXl 1 IX
0000
6
6 2
2 4
3 5
4 6
5 5
4 4
3
RTS CMP CMP CMP CMP CMP CMP 1
1 INH
2
IMM 2 DIR 3 EXT
3
IX2 2
IXl 1 IX
(0)1
2
2 4
3 5
4 6
5 5
4 4
3
2
SBC SBC SBC SBC SBC SBC
2
IMM 2 DIR 3 EXT 3 IX2 2 IXl 1
IX
00.10
11
10
2
2 4
3 5
4 6
5 5
4 4
3
SWI CPX
CPX CPX
CPX CPX
CPX
3
1 INH
2
IMM 2 DIR 3 EXT 3
IX2 2
IXl 1
IX
0011
2
2 4
3 5
4 6
5 5
4 4
3
AND
AND
AND AND AND
AND
4
2
IMM 2 DIR
3 EXT 3 IX2 2
IXl
1
IX
0100
2
2 4
3 5
4 6
5 5
4 4
3
BIT BIT BIT BIT BIT BIT
5
2
IMM 2 DIR
3 EXT 3 IX2 2
IXl 1 IX
0101
2
2 4
3 5
4 6
5 5
4 4
3
LOA
LOA
LOA LOA LOA LOA
6
2
IMM 2
0" 3
EXT 3 IX2 2
IXl
1 IX 0110
2 2
5
4 6 5 7
6 6
5 5
4
TAX
STA STA STA STA STA 7
1 INH
2
DIR 3
EXT 3 IX2 2 IXl 1 IX 0111
2 2 2 2 4 3 5 4 6
5 5
4 4
3
CU::
EOR
EOR EOR
EOR
EOR EOR
8
1 INH 2 IMM 2 DIR
3 EXT 3 IX2 2 IXl 1 IX
1(0)
2 2 2
2 4
3 5
4 6
5 5
4 4
3
SEC ADC ADC ADC
ADC ADC ADC
9
1 INH
2
IMM 2 DIR 3
EXT 3 IX2 2
IXl
1 IX
1001
2
2 2 2 4
3 5
4 6
5 5
4 4
3
CLI ORA ORA ORA
ORA ORA ORA A
1 INH 2 IMM 2
DIR 3 EXT 3 IX2
2
IXl 1 IX
1010
2 2 2 2 4 3 5 4 6
5 5
4 4
3
SEI ADD ADD
ADD
ADD
ADD
ADD
B
1 INH 2 IMM
2
DIR 3
EXT 3 IX2 2 IXl 1 IX
1011
2
2
3
2 4
3 5
4 4
3 3
2
RSP
JMP JMP JMP
JMP
JMP
C
1 INH
2
DIR
3 EXT 3 IX2
2
IXl 1 IX
1100
2 2 8
6 7
5 8 6 9 7 8
6 7 5
NOP
BSR JSR JSR
JSR JSR
JSR 0
1 INH 2
REl 2
DIR 3
EXT 3 IX2
2
IXl 1 IX
1101
*
2 2
2 4
3 5
4 6
5 5 4 4
3
STOP
LOX
LOX
LOX LOX
LOX
LOX
E
1 INH
2
IMM 2 DIR
3 EXT 3 IX2 2 IXl 1
IX 1110
*
2 2
2
5
4 6
5 7
6 6
5 5
4
WAIT TXA STX
STX STX
STX
STX
F
1
INH 1 INH
2
DIR 3 EXT 3
IX2 2
IXl
1 IX 1111
LEGEND
F ... -4---------,.Opcode in Hexadecimal
1111
Cycles. M6805 HMOS __ -J~-';"';';"";:~I-o::::::::::::,;.J.c:::: __
Opcode in Binary
Mnemonic -----+- ...
Bytes--~t.2.._~:2.J-_~~::J
Cycles. M146805 CMOS -----~ ,,-------- Address Mode
10-11/10-12