⚫
The TVS diode can absorb instantaneous high-power pulses, and withstand instantaneous pulse
current peaks up to tens or even hundreds of amperes. The clamp response time is extremely
short. The TVS diode should be placed as close as possible to the power input to ensure that the
surge voltage can be clamped before the pulse is coupled to the adjacent PCB wires.
⚫
The bypass capacitor must be placed close to the power supply pin of the module to filter out
high-frequency noise signals in the power supply.
⚫
For the module power circuit, the PCB routing width must ensure that the 2.5 A current can be
passed safely, and there should be no obvious loop voltage drop. The PCB routing width should
be at least 2.5 mm to ensure that the ground plane of the power supply part is as complete as
possible. In addition, try to make the power cable short and thick.
⚫
Noise-sensitive circuits, such as audio circuits and RF circuits, should be kept away from power
circuits, especially when the DC-DC power supply is used.
⚫
The voltage frequency of the SW pin of the DC-DC power supply is high, and the loop should be
minimized. Sensitive component should be kept far away from the SW pin of the DC-DC
component to prevent noise coupling. Feedback component should be placed as close as
possible to the FB pin and COMP pin.
⚫
The GND pin and bottom pad of the chip must be grounded to ensure good heat dissipation and
noise isolation.
5.1.2 VDD_1P8
VDD_1P8 power is on normally and cannot be turned off even when the module is in sleep mode. Connecting
the module to an external circuit will increase its power consumption in sleep module. It is recommended that
VDD_1P8 is used for level shift only and an ESD protector should be added.
N723-EA provides one VDD_1P8 output. It can provide the 1.8 V voltage and the maximum output
current is 50 mA. It is recommended that DVDD_1P8 is used for level shift and digital IO pull-up power
supply only and an ESD protector should be added.
5.2 Control Interfaces
Power-on/off & reset of the module is
triggered by the low pulse, and is
controlled based on the low pulse
width. The internal interface voltage is
default to VBAT.