Neoway N723-EA - Sdio;Wlan; Figure 5-30 Reference Design of the SDIO Interface with a PHY Chip

N723-EA Hardware User Guide
Chapter 5 Application Interfaces
Copyright © Neoway Technology Co., Ltd. All rights reserved.
53
MDIO
Signal
Pin
I/O
Function description
Remarks
MDIO_CLK
22
DO
MDIO clock
-
MDIO_DATA
23
B
MDIO data input and
output
Connecting an external 4.7
kΩ pull-up resistor is
required.
MDIO supports up to 25 MHz frequency and only 1.8 V level. The following figure shows a reference
design of the SDIO interface with a PHY chip:
Figure 5-30 Reference design of the SDIO interface with a PHY chip:
PHY
N723-EA
Module
VDD_1P8
MDIO_DATA
MDIO_CLK
MDIO_DATA
MDIO_CLK
4.7KΩ
R1
5.4.2 SDIO/WLAN
Signal
Pin
I/O
Function description
Remarks
WLAN_SDIO_CMD
54
B
SDIO command
Leave this pin floating if it is not
used.
WLAN_SDIO_CLK
55
DO
SDIO clock
Leave this pin floating if it is not
used.
WLAN_SDIO_DATA0
56
B
SDIO data bit 0
Leave this pin floating if it is not
used.
WLAN_SDIO_DATA1
57
B
SDIO data bit 1
Leave this pin floating if it is not
used.
WLAN_SDIO_DATA2
58
B
SDIO data bit 2
Leave this pin floating if it is not
used.