Neoway N723-EA - Figure 5-31 SDIO Reference Design

N723-EA Hardware User Guide
Chapter 5 Application Interfaces
Copyright © Neoway Technology Co., Ltd. All rights reserved.
54
WLAN_SDIO_DATA3
59
B
SDIO data bit 3
Leave this pin floating if it is not
used.
WAKE_ON_WIRELESS
60
DO
WLAN wakeup control
Leave this pin floating if it is not
used.
WLAN_SLEEP_CLK
61
DO
Wi-Fi sleep clock
Clock frequency: 32 KHz.
Leave this pin floating if it is not
used.
WLAN_EN
62
DO
WLAN enable control
Leave this pin floating if it is not
used.
WLAN_PWR_EN
63
DO
Control of the external
power supply for WLAN
Leave this pin floating if it is not
used.
The SDIO interface supports only 1.8 V voltage and SDIO2.0 and SDIO3.0 for Wi-Fi connections. Its
clock supports up to HS200-200MHz, SDR50-100MHz or DDR50-50MHz frequency. The following
figure shows a reference design of the SDIO interface:
Figure 5-31 SDIO reference design
WLAN Device
N723-EA
Module
WLAN_SDIO_CLK
WLAN_SDIO_CMD
WLAN_SDIO_DATA0
WLAN_SDIO_DATA1
WLAN_SDIO_DATA2
WLAN_SDIO_DATA3
WLAN_EN
WLAN_SLEEP_CLK
WAKE_ON_WIRELESS
SDIO_CLK
SDIO_CMD
SDIO_DATA0
SDIO_DATA1
SDIO_DATA2
SDIO_DATA3
WLAN_EN
SLEEP_CLK
WAKE_UP
WLAN_PWR_EN VCC
EN
VIN VOUT
GND
U1
V_IN
C1
C2
R1
R2
C3
DNI
C4
C5
V_WLAN
V_WLAN
Design Guideline:
⚫
If the load has a pull-up resistor requirement pay attention to the resistance. It is recommended
to use VDD_1P8 of the module.