USB and PCIe
PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX DG-10931-001_v0.1 | 21
Module Pin
Recommended
169 PCIE1_RX0_P
HS_UPHY0_L3_RX_
P
PCIe x1
conn/device (i.e.
M.2 Key E)
172 PCIE1_TX0_N
HS_UPHY0_L3_TX_
N
PCIe #1 Transmit 0 (PCIe Ctrl #1 Lane 0) Output PCIe PHY
174 PCIE1_TX0_P HS_UPHY0_L3_TX_P
183 PCIE1_RST*
GP178_PCIE1_RST_
N
PCIe #1 Reset (PCIe Ctrl #1). 4.7kΩ pull-up
to 3.3V on the module.
Output
Open
Drain 3.3V
182
PCIE1_CLKRE
Q*
GP177_PCIE1_
CLKREQ_N
PCIE #1 Clock Request (PCIe Ctrl #1).
47kΩ pull-up to 3.3V on the module.
Bidir
Open
Drain 3.3V
173 PCIE1_CLK_N SF_PCIE1_CLK_N
PCIe #1 Reference Clock (PCIe Ctrl #1) Output PCIe PHY
175 PCIE1_CLK_P SF_PCIE1_CLK_P
40 CSI4_D2_N
HS_UPHY2_L0_RX_
N
PCIe 2 Receive 0– (PCIe Ctrl #7 Lane 0)
PCIe x2 (Ctrl #7)
or 2 x PCIe x1
(Ctrl #7 and Ctrl
#9)
Input PCIe PHY
42 CSI4_D2_P
HS_UPHY2_L0_RX_
P
PCIe 2 Receive 0+ (PCIe Ctrl #7 Lane 0) Input PCIe PHY
58 CSI4_D1_N
HS_UPHY2_L1_RX_
N
PCIe #2 Receive 1– (PCIe Ctrl #7 Lane 1) or
PCIe #3 Receive 0– (PCIe Ctrl #9 Lane 0)
Output PCIe PHY
60 CSI4_D1_P
HS_UPHY2_L1_RX_
P
PCIe #2 Receive 1+ (PCIe Ctrl #7 Lane 1) or
PCIe #3 Receive 0+ (PCIe Ctrl #9 Lane 0)
Output PCIe PHY
46 CSI4_D0_N
HS_UPHY2_L0_TX_
N
PCIe #2 Transmit 0– (PCIe Ctrl #7 Lane 0) Output PCIe PHY
48 CSI4_D0_P HS_UPHY2_L0_TX_P PCIe #2 Transmit 0+ (PCIe Ctrl #7 Lane 0) Output PCIe PHY
64 CSI4_D3_N
HS_UPHY2_L1_TX_
N
PCIe #2 Transmit 1– (PCIe Ctrl #7 Lane 1)
or PCIe #3 Transmit 0– (PCIe Ctrl #9 Lane
0)
Output PCIe PHY
66 CSI4_D3_P HS_UPHY2_L1_TX_P
PCIe #2 Transmit 1+ (PCIe Ctrl #7 Lane 1)
or PCIe #3 Transmit 0+ (PCIe Ctrl #9 Lane
0)
Output
Open
Drain 3.3V
52 CSI4_CLK_N SF_PCIE7_CLK_P PCIe #2 Reference Clock– (PCIe Ctrl #7) Input
Open
Drain 3.3V
54 CSI4_CLK_P SF_PCIE7_CLK_N PCIe #2 Reference Clock+ (PCIe Ctrl #7) Input PCIe PHY
219 SDMMC_DAT0
GP188_PCIE7_RST_
N
PCIe #2 Reset (PCIe Ctrl #7). 4.7kΩ pull-up
to 3.3V on the module.
Output PCIe PHY
221 SDMMC_DAT1
GP187_PCIE7_
CLKREQ_N
PCIE #2 Clock Request (PCIe Ctrl #7).
47kΩ pull-up to 3.3V on the module.
Bidir
Open
Drain 3.3V
229 SDMMC_CLK SF_PCIE9_CLK_P PCIe #3 Reference Clock– (PCIe Ctrl #9)
PCIe x1 (Ctrl #3)
Output
Open
Drain 3.3V
227 SDMMC_CMD SF_PCIE9_CLK_N PCIe #3 Reference Clock+ (PCIe Ctrl #9) Output PCIe PHY
223 SDMMC_DAT2
GP192_PCIE9_RST_
N
PCIe #3 Reset (PCIe Ctrl #9). 4.7kΩ pull-up
to 3.3V on the module.
Output PCIe PHY
225 SDMMC_DAT3
GP191_PCIE9_
CLKREQ_N
PCIE #3 Clock Request (PCIe Ctrl #9).
47kΩ pull-up to 3.3V on the module.
Bidir PCIe PHY
179 PCIE_WAKE*
GP185_PCIE_WAKE
_N
PCIe Wake. 47kΩ pull-up to 3.3V on the
module.
Shared between
PCIe interfaces.
Input
Open
Drain 3.3V
161 USBSS_RX_N
HS_UPHY0_L0_RX_
N
USB SS Receive (USB 3.2 Port #0) Input
USB SS
PHY