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PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX DG-10931-001_v0.1 | 41
The following figure shows an example of a DP++ connection.
Figure 9-2. DP++ Connection Example
0. 1uF
0. 1uF
0. 1uF
0. 1uF
0. 1uF
0. 1uF
0. 1uF
0. 1uF
0. 1uF
0. 1uF
VDD_3 V3 _EDP
DP
Conn
.
PWR
PWR_RET
HPD
AUXN
GND
AUXP
CEC_DP
MODE
LA NE _3 N
GND
LA NE _3 P
LA NE _2 N
GND
LA NE _2 P
LA NE _1 N
GND
LA NE _1 P
LA NE _0 N
GND
LA NE _0 P
1
3
5
11
7
9
13
15
17
19
2
10
12
6
8
14
16
18
4
20
Jetson
SoC
– DP/HDMI
HDMI_CEC
DP1_HPD
DP1_AUX_N
DP1_AUX_P
DP1_TXD3_N
DP1_TXD3_P
DP1_TXD2_N
DP1_TXD2_P
DP1_TXD1_N
DP1_TXD1_P
DP1_TXD0_N
DP1_TXD0_P
96
100
98
65
63
71
69
77
83
81
75
0. 1uF
VDD_3 V3 _SY S
BUCK_3V3_PG
Load Switch
EN
IN
OUT
HS_DISP0_HDMI_D2_DP0_P
HS_DISP0_HDMI_D2_DP0_N
HS_DISP0_HDMI_D1_DP1_P
HS_DISP0_HDMI_D1_DP1_N
HS_DISP0_HDMI_D0_DP2_P
HS_DISP0_HDMI_D0_DP2_N
HS_DISP0_HDMI_CK_DP3_P
HS_DISP0_HDMI_CK_DP3_N
SF_DPAUX01_P
SF_DPAUX01_N
GP7 4_ HP D 0_ N
PI3AUX221ZTAEX
HPD1
VRE F1
VRE F2
SEL
AUX1 _P
AUX1 _N
AUX2 A_P
AUX2A
_N
HPD2
VDD_1 V8
SN 74L VC
1G 04Q 1
AUX2 B_P
AUX2 B_
N
0Ω
22 0pF 22 0pF
G
S
D
VDD_3 V3 _SY S
16 2kΩ, 1%
32.4kΩ, 1%
94
GP05_HDMI_CEC
LIN E17
LIN E15
LIN E13
LIN E11
LIN E10
LIN E9
LIN E8
LIN E7
LIN E6
LIN E5
LIN E4
LIN E3
LIN E2
LIN E1
GND
ESD MG20 40MUTAG
9.1.1 eDP and DP Routing Guidelines
The following routing requirements meet the eDP and DP routing guidelines.
Figure 9-3. eDP and DP Differential Main Link Topology
Jetson
eDP
Conn
SoC
Pkg
DP
Dri ve r
P
N
Com m on Mode
Cho kes & ES D
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