Nvidia Jetson Orin NX - Page 5

PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX DG-10931-001_v0.1 | v
List of Figures
Figure 2-1. Jetson Orin NX Block Diagram .............................................................................. 4
Figure 5-1. Jetson Orin NX Module Installed in SODIMM Connector ................................... 12
Figure 5-2. Module to Connector Assembly Diagram ........................................................... 12
Figure 6-1. System Power and Control Block Diagram ........................................................ 16
Figure 6-2. System Power and Control Block Diagram ........................................................ 16
Figure 6-3. Power Up Sequence No Power Button – Auto Power On .................................. 17
Figure 6-4. Power Up Sequence with Power Button ............................................................. 17
Figure 6-5. Power Down Initiated by SHUTDOWN_REQ* Assertion ..................................... 18
Figure 6-6. Power Down Sudden Power Loss ....................................................................... 18
Figure 7-1. USB Micro B USB Device and Recovery Connection Example .......................... 23
Figure 7-2. USB SS Type A Host Only Connection Example ................................................. 23
Figure 7-3. IL/NEXT Plot ......................................................................................................... 27
Figure 7-4. TDR Plot ................................................................................................................ 27
Figure 7-5. Via Topology .......................................................................................................... 27
Figure 7-6. Component Order ................................................................................................. 27
Figure 7-7. Component Placement ........................................................................................ 28
Figure 7-8. ESD Layout Recommendations ........................................................................... 28
Figure 7-9. PCIe Root Port Connections Example ................................................................. 30
Figure 7-10. PCIe Endpoint Connections Example .................................................................. 31
Figure 7-11. Zig-Zag Routing Example .................................................................................... 33
Figure 7-12. Insertion Loss S-Parameter Plot SDD21 ............................................................ 34
Figure 7-13. Insertion Loss S-Parameter Plot SDD11 ............................................................ 34
Figure 7-14. AC Cap Voiding ..................................................................................................... 34
Figure 7-15. Connector Voiding ................................................................................................ 34
Figure 8-1. Jetson Orin NX Ethernet Connections ................................................................ 37
Figure 8-2. Gigabit Ethernet Magnetics and RJ45 Connections ........................................... 38
Figure 9-1. DP and eDP Connection Example ....................................................................... 40
Figure 9-2. DP++ Connection Example .................................................................................. 41
Figure 9-3. eDP and DP Differential Main Link Topology ..................................................... 41
Figure 9-4. S-Parameter Up to HBR2 .................................................................................... 44
Figure 9-5. S-Parameter Up to HBR3 .................................................................................... 44
Figure 9-6. Via Topology #1 .................................................................................................... 45
Figure 9-7. Via Topology #2 .................................................................................................... 45
Figure 9-8. HDMI Connection Example .................................................................................. 46
Figure 9-9. HDMI CLK and Data Topology ............................................................................. 47
Figure 9-10. IL/FEXT Plot .......................................................................................................... 50
Figure 9-11. TDR Plot ................................................................................................................ 50