Nvidia Jetson Orin NX - Page 56

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PRELIMINARY INFORMATION
NVIDIA Jetson Orin NX DG-10931-001_v0.1 | 48
Parameter
Requirement
Units
Notes
Min Trace spacing (Pair-Pair)
Stripline: 2.1
Stripline: 1.4b/2.0
Microstrip: 2.1
Microstrip: 1.4b/2.0
4x
3x
7x
5x to 7x
dielectric
For Stripline, this is 3x of the thinner of
above and below.
Trace spacing (Main link to DDC)
Stripline
Microstrip
3x
5x
dielectric
For Stripline, this is 3x of the thinner of
above and below.
Max Total Delay (2.1)
Stripline (4x spacing)
Microstrip (7x spacing)
76 (535)
63.5 (375)
mm (ps)
Propagation delay: 6.9ps/mm
assumption for Stripline, 5.9ps/mm for
Microstrip.
Max Total Delay (1.4b/2.0)
Stripline
Microstrip (5x spacing)
Microstrip (7x spacing)
101 (700)
88.5 (525)
101 (600)
mm (ps)
Propagation delay: 6.9ps/mm
assumption for Stripline, 5.9ps/mm for
Microstrip.
Max intra-pair (within pair) skew
0.15 (1)
mm (ps)
See notes 1, 2, and 3
Max inter-pair (pair to pair) skew
150
ps
See notes 1, 2, and 3
Max GND transition via distance
1x
Diff pair via pitch
For signals switching reference layers,
add one or two ground stitching vias. It is
recommended they be symmetrical to
signal vias.
Via
Topology
- Y-pattern is recommended
- keep symmetry
Xtalk suppression is the best by Y-
pattern. Also it can reduce the limit of
pair-pair distance. Need review
(NEXT/FEXT check) if via placement is
not Y-pattern. See
Figure 9-12
Minimum impedance dip
97
92
Ω@200ps
Ω@35ps
Recommended via dimension
drill/pad
Antipad
via pitch
200/400
840
880
uM
GND via
Place GND via as symmetrically as
possible to data pair vias. Up to four
signal vias (2 diff pairs) can share a
single GND return via
GND via is used to maintain return path,
while its Xtalk suppression is limited
Connector pin via
The break-in trace to the connector pin
via should be routed on the BOTTOM in
order to avoid via stub effect
Equal spacing (0.8mm) between
adjacent signal vias.
The x-axis distance between signal and
GND via should be > 0.6mm
See Figure 9-13
Max # of vias
PTH via
u-via
2 if all vias are PTH via
Not limited if total channel loss
meets IL spec.
No breakout: ≤ 3 vias: See Figure 9-14
Breakout on the same layer as main
trunk: ≤ 4 vias: See Figure 9-15
Max via stub length
0.4
mm
long via stub requires review (IL and
resonance dip check)
Topology
The main route via dimensions should comply with the via structure rules (See via
section)
See topology in Figure 9-9
For the connector pin vias, follow the rules for the connector pin vias (See via section)
The traces after main route via should be routed as 100Ω differential or as uncoupled
50ohm SE traces on PCB top or bottom.
Max distance from R
PD
to main trace (seg B)
1
mm
Max distance from AC cap to RPD stubbing
point (seg A)
~0
mm
Max distance between ESD and signal via
3
mm
Add-on Components
Example of a case where space is limited for
placing components.
Top: See Figure 9-16
Bottom: See Figure 9-17