Flash Memory System and Programming 280 May 03, 2004
Philips Semiconductors Preliminary User Manual
LPC2119/2129/2194/2292/2294ARM-based Microcontroller
0x7fffffb0 A rm_prefetchabort_handler
0x7fffffc0 A rm_dataabort_handler
0x7fffffd0 A rm_irqhandler
0x7fffffe0 A rm_irqhandler2
0x7ffffff0 T iap_entry
As per the ARM specification (The ARM Thumb Procedure Call Standard SWS ESPC 0002 A-05) up to 4 parameters can be
passed in the r0, r1, r2 and r3 registers respectively. Additional parameters are passed on the stack. Up to 4 parameters can be
returned in the r0, r1, r2 and r3 registers respectively. Additional parameters are returned indirectly via memory. Some of the IAP
calls require more than 4 parameters. If the ARM suggested scheme is used for the parameter passing/returning then it might
create problems due to difference in the C compiler implementation from different vendors. The suggested parameter passing
scheme reduces such risk.
The flash memory is not accessible during a write or erase operation. IAP commands, which results in a flash write/erase
operation, use 32 bytes of space in the top portion of the on-chip RAM for execution. The user program should not be use this
space if IAP flash programming is permitted in the application.
Table 214: IAP Command Summary
IAP Command Command Code Described in
Prepare sector(s) for write operation 50 Table 215
Copy RAM to Flash 51 Table 216
Erase sector(s) 52 Table 217
Blank check sector(s) 53 Table 218
Read Part ID 54 Table 219
Read Boot code version 55 Table 220
Compare 56 Table 221
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