LPC2119/2129/2292/2294 Memory Addressing 49 May 03, 2004
Philips Semiconductors Preliminary User Manual
LPC2119/2129/2194/2292/2294ARM-based Microcontroller
Figure 3: Peripheral Memory Map
Figures 3 through 5 show different views of the peripheral address space. Both the AHB and VPB peripheral areas are 2
megabyte spaces which are divided up into 128 peripherals. Each peripheral space is 16 kilobytes in size. This allows simplifying
the address decoding for each peripheral. All peripheral register addresses are word aligned (to 32-bit boundaries) regardless of
their size. This eliminates the need for byte lane mapping hardware that would be required to allow byte (8-bit) or half-word (16-
bit) accesses to occur at smaller boundaries. An implication of this is that word and half-word registers must be accessed all at
once. For example, it is not possible to read or write the upper byte of a word register separately.
AHB Peripherals
VPB Peripherals
4.0 GB
0xFFFF FFFF
3.75 GB
0xE000 0000
Reserved
Reserved
Notes:
- AHB section is
128 x 16 kB blocks
(totaling 2 MB).
- VPB section is
128 x 16 kB blocks
(totaling 2 MB).
0xFFE0 0000
0xFFDF FFFF
3.5 GB
0xF000 0000
0xEFFF FFFF
0xE020 0000
0xE01F FFFF
4.0 GB - 2 MB
3.5 GB + 2 MB
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