Quectel EG25-G User Manual

LTE Module Series
EG25-G Hardware Design
EG25-G_Hardware_Design 51 / 100
 It is important to route the SDIO signal traces with total grounding. The impedance of SDIO data
trace is 50Ω (±10%).
 Make sure the adjacent trace spacing is two times of the trace width and the load capacitance of
SDIO bus should be less than 15pF.
 It is recommended to keep the trace length difference between CLK and DATA/CMD less than 1mm
and the total routing length less than 50mm. The total trace length inside the module is 27mm, so the
exterior total trace length should be less than 23mm.
3.14. Wireless Connectivity Interfaces
EG25-G supports a low-power SDIO 3.0 interface for WLAN and a UART/PCM interface for BT.
The following table shows the pin definition of wireless connectivity interfaces.
Table 16: Pin Definition of Wireless Connectivity Interfaces
Pin Name
Pin No.
I/O
Description
Comment
WLAN Part
SDC1_DATA3
129
IO
WLAN SDIO data bus D3
1.8V power domain
SDC1_DATA2
130
IO
WLAN SDIO data bus D2
1.8V power domain
SDC1_DATA1
131
IO
WLAN SDIO data bus D1
1.8V power domain
SDC1_DATA0
132
IO
WLAN SDIO data bus D0
1.8V power domain
SDC1_CLK
133
DO
WLAN SDIO bus clock
1.8V power domain
SDC1_CMD
134
IO
WLAN SDIO bus command
1.8V power domain
WLAN_EN
136
DO
WLAN function control via FC20
module.
1.8V power domain
Active high.
Cannot be pulled up before
startup.
Coexistence and Control Part
WLAN_SLP_CLK
118
DO
WLAN sleep clock
PM_ENABLE
127
DO
WLAN power control.
1.8V power domain
Active high.
WAKE_ON_
WIRELESS
135
DI
Wake up the host (EG25-G
module) by FC20 module.
1.8V power domain

Quectel EG25-G Specifications

General

Brand	Quectel
Model	EG25-G
Category	GSM/GPRS Modules
Language	English