Figure 28: Reference Circuit of SGMII Interface with PHY AR8033 Application
In order to enhance the reliability and availability in customers’ applications, please follow the criteria
below in the Ethernet PHY circuit design:
Keep SGMII data and control signals away from other sensitive circuits/signals such as RF circuits,
analog signals, etc., as well as noisy signals such as clock signals, DCDC signals, etc.
Keep the maximum trace length less than 10-inch and keep skew on the differential pairs less than
20mil.
The differential impedance of SGMII data trace is 100Ω±10%, and the reference ground of the area
should be complete.
Make sure the trace spacing between SGMII RX and TX is at least 3 times of the trace width, and the
same to the adjacent signal traces.
3.16. ADC Interfaces
The module provides two analog-to-digital converter (ADC) interfaces. AT+QADC=0 command can be
used to read the voltage value on ADC0 pin. AT+QADC=1 command can be used to read the voltage
value on ADC1 pin. For more details about these AT commands, please refer to document [2].
In order to improve the accuracy of ADC, the trace of ADC should be surrounded by ground.
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