Quectel EG25-G - Table 17: Pin Definition of Sgmii Interface

LTE Module Series
EG25-G Hardware Design
EG25-G_Hardware_Design 55 / 100
The following table shows the pin definition of SGMII interface.
Table 17: Pin Definition of SGMII Interface
Pin Name
Pin No.
I/O
Description
Comment
Control Signal Part
EPHY_RST_N
119
DO
Ethernet PHY reset
1.8V/2.85V power domain
EPHY_INT_N
120
DI
Ethernet PHY interrupt
1.8V power domain
SGMII_MDATA
121
IO
SGMII MDIO (Management Data
Input/Output) data
1.8V/2.85V power domain
SGMII_MCLK
122
DO
SGMII MDIO (Management Data
Input/Output) clock
1.8V/2.85V power domain
USIM2_VDD
128
PO
SGMII MDIO pull-up power
source
Configurable power source.
1.8V/2.85V configurable.
External pull-up power source for
SGMII MDIO pins.
SGMII Signal Part
SGMII_TX_M
123
AO
SGMII transmission-minus
Connect with a 0.1uF capacitor,
and close to the PHY side.
SGMII_TX_P
124
AO
SGMII transmission-plus
SGMII_RX_P
125
AI
SGMII receiving-plus
Connect with a 0.1uF capacitor,
and close to EG25-G module.
SGMII_RX_M
126
AI
SGMII receiving-minus
The following figure shows the simplified block diagram for Ethernet application.
Module
AR8033
Ethernet
Transformer
RJ45
SGMII
Control
MDI
Figure 27: Simplified Block Diagram for Ethernet Application