MC9S08QE128 MCU Series Reference Manual, Rev. 2
Freescale Semiconductor 145
Chapter 8
Central Processor Unit (S08CPUV4)
8.1 Introduction
This section provides summary information about the registers, addressing modes, and instruction set of
the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference
Manual, volume 1, Freescale Semiconductor document order number HCS08RMV1/D.
The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU. Several
instructions and enhanced addressing modes were added to improve C compiler efficiency and to support
a new background debug system which replaces the monitor mode of earlier M68HC08 microcontrollers
(MCU).
8.1.1 Features
Features of the HCS08 CPU include:
• Object code fully upward-compatible with M68HC05 and M68HC08 Families
• 64-KB CPU address space with banked memory management unit for greater than 64 KB
• 16-bit stack pointer (any size stack anywhere in 64-KB CPU address space)
• 16-bit index register (H:X) with powerful indexed addressing modes
• 8-bit accumulator (A)
• Many instructions treat X as a second general-purpose 8-bit register
• Seven addressing modes:
— Inherent — Operands in internal registers
— Relative — 8-bit signed offset to branch destination
— Immediate — Operand in next object code byte(s)
— Direct — Operand in memory at 0x0000–0x00FF
— Extended — Operand anywhere in 64-Kbyte address space
— Indexed relative to H:X — Five submodes including auto increment
— Indexed relative to SP — Improves C efficiency dramatically
• Memory-to-memory data move instructions with four address mode combinations
• Overflow, half-carry, negative, zero, and carry condition codes support conditional branching on
the results of signed, unsigned, and binary-coded decimal (BCD) operations
• Efficient bit manipulation instructions
• Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions
• STOP and WAIT instructions to invoke low-power operating modes
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