MC9S08QE128 MCU Series Reference Manual, Rev. 2
Freescale Semiconductor 39
Chapter 3
Modes of Operation
3.1 Introduction
The operating modes of the MC9S08QE128 Series are described in this chapter. Entry into each mode,
exit from each mode, and functionality while in each of the modes are described.
3.2 Features
• Active background mode for code development
• Run mode — CPU clocks can be run at full speed and the internal supply is fully regulated.
• LPRUN mode — CPU clocks are restricted to a maximum of 250 kHz, peripheral clocks are
restricted to a maximum of 125 kHz, and the internal voltage regulator is in standby
• Wait mode — CPU shuts down to conserve power; system clocks are running and full regulation
is maintained
• LPWAIT mode — CPU shuts down to conserve power; peripheral clocks are restricted to 125 kHz
maximum and the internal voltage regulator is in standby
• Stop modes — System clocks are stopped and voltage regulator is in standby
— Stop3 — All internal circuits are powered for fast recovery
— Stop2 — Partial power down of internal circuits, RAM content is retained; I/O states are held
3.3 Run Mode
This is the normal operating mode for the MC9S08QE128 Series. In this mode, the CPU executes code
from internal memory with execution beginning at the address fetched from memory at 0xFFFE–0xFFFF
after reset.
3.3.1 Low Power Run Mode (LPRun)
In the low power run mode, the on-chip voltage regulator is put into its standby state. In this state, the
power consumption is reduced to a minimum that still allows CPU functionality. Power consumption is
reduced the most by disabling the clocks to all unused peripherals by clearing the corresponding bits in the
SCGC1 and SCGC2 registers.
Before entering this mode, the following conditions must be met:
• FBELP is the selected clock mode for the ICS (See the FBELP section in Chapter 11, “Internal
Clock Source (S08ICSV3).”
• The HGO bit in the ICSC2 register is clear.
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