MC9S08QE128 MCU Series Reference Manual, Rev. 2
Freescale Semiconductor 9
Contents
Section Number Title Page
Chapter 1
Device Overview
1.1 Devices in the MC9S08QE128 Series .............................................................................................19
1.2 MCU Block Diagram ......................................................................................................................20
1.3 System Clock Distribution ..............................................................................................................23
Chapter 2
Pins and Connections
2.1 Device Pin Assignment ...................................................................................................................25
2.2 Recommended System Connections ...............................................................................................31
2.2.1 Power ................................................................................................................................33
2.2.2 Oscillator ...........................................................................................................................33
2.2.3
RESET and RSTO ............................................................................................................33
2.2.4 Background / Mode Select (BKGD/MS) ..........................................................................34
2.2.5 ADC Reference Pins (V
REFH
, V
REFL
) ..............................................................................35
2.2.6 General-Purpose I/O and Peripheral Ports ........................................................................35
Chapter 3
Modes of Operation
3.1 Introduction .....................................................................................................................................39
3.2 Features ...........................................................................................................................................39
3.3 Run Mode ........................................................................................................................................39
3.3.1 Low Power Run Mode (LPRun) .......................................................................................39
3.4 Active Background Mode ................................................................................................................41
3.5 Wait Mode .......................................................................................................................................42
3.5.1 Low Power Wait Mode (LPWait) ......................................................................................42
3.6 Stop Modes ......................................................................................................................................42
3.6.1 Stop2 Mode .......................................................................................................................43
3.6.2 Stop3 Mode .......................................................................................................................44
3.6.3 Active BDM Enabled in Stop Mode .................................................................................45
3.6.4 LVD Enabled in Stop Mode ..............................................................................................45
3.6.5 Stop modes in Low Power Run Mode ..............................................................................45
3.7 Mode Selection ................................................................................................................................45
3.7.1 On-Chip Peripheral Modules in Stop and Low Power Modes ..........................................48
Chapter 4
Memory
4.1 MC9S08QE128 Series Memory Map .............................................................................................51
4.2 Reset and Interrupt Vector Assignments .........................................................................................53
To Next Page
Loading...