ROHS MC9S08QE128 - Chapter 1 Device Overview

To Next Page

To Previous Page

Chapter 1 Device Overview

MC9S08QE128 MCU Series Reference Manual, Rev. 2

20 Freescale Semiconductor

1.2 MCU Block Diagram

The block diagram in Figure 1-1 shows the structure of the MC9S08QE128 Series MCU.

Main Page

Default Chapter8
- Table of Contents8
Section Number Title Page9
- Devices in the MC9S08QE128 Series18
Chapter 1 Device Overview19
- MCU Block Diagram20
- System Clock Distribution23
- Pins and Connections24
- Device Pin Assignment24
Chapter 2 Pins and Connections25
- Recommended System Connections31
- Refh Refl34
  - ADC Reference Pins35
- Modes of Operation 3.1 Introduction38
- Features38
- Run Mode38
  - Low Power Run Mode (Lprun)39
Chapter 3 Modes of Operation39
- Active Background Mode41
- Wait Mode41
  - Low Power Wait Mode (Lpwait)42
- Stop Modes42
  - Stop2 Mode42
  - Stop3 Mode44
- Mode Selection44
- MC9S08QE128 Series Memory Map51
Chapter 4 Memory51
- Reset and Interrupt Vector Assignments53
- Register Addresses and Bit Assignments55
- Memory Management Unit63
- Ram69
- Flash69
- Introduction89
- Features89
- MCU Reset89
- Computer Operating Properly (COP) Watchdog90
- Interrupts91
Chapter 592
- Interrupt Stack Frame92
- External Interrupt Request (IRQ) Pin92
- Interrupt Vectors, Sources, and Local Masks93
- Low-Voltage Detect (LVD) System96
- Peripheral Clock Gating96
- Reset, Interrupt, and System Control Registers and Control Bits98
Chapter 6 Parallel Input/Output Control111
- Port Data and Data Direction111
- Pull-Up, Slew Rate, and Drive Strength112
- Port Data Set, Clear and Toggle Data Registers113
- Pin Behavior in Stop Modes114
- Parallel I/O and Pin Control Registers114
Chapter 7 Keyboard Interrupt (S08KBIV2)139
- Introduction139
- External Signal Description140
- Register Deﬁnition141
- Functional Description142
Chapter 8 Central Processor Unit (S08CPUV4)145
- Introduction145
  - Features145
- Programmer's Model and CPU Registers146
- Addressing Modes149
- Special Operations151
- HCS08 Instruction Set Summary155
Chapter 9 Analog Comparator 3V (ACMPVLPV1)167
- Introduction167
- External Signal Description171
- Register Deﬁnition171
  - Acmpx Status and Control Register (Acmpxsc)172
- Functional Description173
Chapter 10 Analog-To-Digital Converter (S08ADC12V1)175
- Introduction175
- External Signal Description180
- Register Deﬁnition181
- Functional Description190
- Initialization Information195
  - ADC Module Initialization Example195
- Application Information197
  - External Pins and Routing197
  - Sources of Error199
Chapter 11 Internal Clock Source (S08ICSV3)203
- Introduction203
- External Signal Description207
- Register Deﬁnition207
- Functional Description212
Chapter 12 Inter-Integrated Circuit (S08IICV2)217
- Introduction217
- External Signal Description220
  - SCL - Serial Clock Line220
  - SDA - Serial Data Line220
- Register Deﬁnition221
- Functional Description228
- Resets233
- Interrupts233
- Initialization/Application Information235
Chapter 13 Real-Time Counter (S08RTCV1)237
- Introduction237
- External Signal Description241
- Register Deﬁnition241
- Functional Description244
  - RTC Operation Example245
- Initialization/Application Information245
Chapter 14 Serial Communications Interface (S08SCIV4)247
- Introduction247
- Register Deﬁnition253
- Functional Description260
Chapter 15 Serial Peripheral Interface (S08SPIV3)267
- Introduction267
- External Signal Description272
- Modes of Operation273
  - SPI in Stop Modes273
- Register Deﬁnition273
- Functional Description278
Chapter 16 Timer/Pulse-Width Modulator (S08TPMV3)283
- Introduction283
- Signal Description288
  - Detailed Signal Descriptions288
- Register Deﬁnition292
- Functional Description298
  - Counter298
  - Channel Mode Selection300
- Reset Overview303
  - General303
  - Description of Reset Operation303
- Interrupts303
  - Description of Interrupt Operation304
Chapter 17 Development Support307
- Introduction307
- Background Debug Controller (BDC)308
- Register Deﬁnition315
  - BDC Registers and Control Bits316
  - System Background Debug Force Reset Register (SBDFR)318
Chapter 18 Debug Module (DBG) (128K)321
- Introduction321
- Signal Description322
- Memory Map and Registers323
  - Module Memory Map323
  - Register Descriptions325
- Functional Description338
- Resets344
- Interrupts345
- Electrical Speciﬁcations345

ROHS MC9S08QE128 - Chapter 1 Device Overview

Table of Contents