Inter-Integrated Circuit (S08IICV2)
MC9S08QE128 MCU Series Reference Manual, Rev. 2
222 Freescale Semiconductor
12.3.2 IIC Frequency Divider Register (IICxF)
For example if the bus speed is 8MHz, the table below shows the possible hold time values with different
ICR and MULT selections to achieve an IIC baud rate of 100kbps.
76543210
R
MULT ICR
W
Reset 00000000
Figure 12-4. IIC Frequency Divider Register (IICxF)
Table 12-3. IICxF Field Descriptions
Field Description
7:6
MULT
IIC Multiplier Factor — The MULT bits define the multiplier factor mul. This factor is used along with the SCL
divider to generate the IIC baud rate. The multiplier factor mul as defined by the MULT bits is provided below.
00 mul = 01
01 mul = 02
10 mul = 04
11 Reserved
5:0
ICR
IIC Clock Rate — The ICR bits are used to prescale the bus clock for bit rate selection. These bits and the MULT
bits are used to determine the IIC baud rate, the SDA hold time, the SCL Start hold time and the SCL Stop hold
time. Table 12-4 provides the SCL divider and hold values for corresponding values of the ICR.
The SCL divider multiplied by multiplier factor mul is used to generate IIC baud rate.
IIC baud rate = bus speed (Hz)/(mul * SCL divider) Eqn. 12-1
SDA hold time is the delay from the falling edge of SCL (IIC clock) to the changing of SDA (IIC data).
SDA hold time = bus period (s) * mul * SDA hold value Eqn. 12-2
SCL Start hold time is the delay from the falling edge of SDA (IIC data) while SCL is high (Start condition) to the
falling edge of SCL (IIC clock).
SCL Start hold time = bus period (s) * mul * SCL Start hold value Eqn. 12-3
SCL Stop hold time is the delay from the rising edge of SCL (IIC clock) to the rising edge of SDA
SDA (IIC data) while SCL is high (Stop condition).
SCL Stop hold time = bus period (s) * mul * SCL Stop hold value Eqn. 12-4
MULT ICR
Hold times (μs)
SDA SCL Start SCL Stop
0x2 0x00 3.500 4.750 5.125
0x1 0x07 2.500 4.250 5.125
0x1 0x0B 2.250 4.000 5.250
0x0 0x14 2.125 4.000 5.250
0x0 0x18 1.125 3.000 5.500
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