Internal Clock Source (S08ICSV3)
MC9S08QE128 MCU Series Reference Manual, Rev. 1.11
210 Freescale Semiconductor
11.3.4 ICS Status and Control (ICSSC)
Table 11-5. ICS Trim Register Field Descriptions
Field Description
7:0
TRIM
ICS Trim Setting — The TRIM bits control the internal reference clock frequency by controlling the internal
reference clock period. The bits’ effect are binary weighted (i.e., bit 1 will adjust twice as much as bit 0).
Increasing the binary value in TRIM will increase the period, and decreasing the value will decrease the period.
An additional fine trim bit is available in ICSSC as the FTRIM bit.
7 654 3 210
R DRST
DMX32
IREFST CLKST OSCINIT
FTRIM
1
1
FTRIM is loaded during reset from a factory programmed location when not in any BDM mode. If in a BDM mode, FTRIM
gets loaded with a value of 1’b0.
W DRS
Reset: 0 0 0 1 0 0 0
Figure 11-6. ICS Status and Control Register (ICSSC)
Table 11-6. ICS Status and Control Register Field Descriptions
Field Description
7-6
DRST
DRS
DCO Range Status — The DRST read field indicates the current frequency range for the FLL output, DCOOUT.
See Table 11-7. The DRST field does not update immediately after a write to the DRS field due to internal
synchronization between clock domains. Writing the DRS bits to 2’b11 will be ignored and the DRST bits will
remain with the current setting.
DCO Range Select — The DRS field selects the frequency range for the FLL output, DCOOUT. Writes to the
DRS field while the LP bit is set are ignored.
00 Low range.
01 Mid range.
10 High range.
11 Reserved.
5
DMX32
DCO Maximum frequency with 32.768 kHz reference — The DMX32 bit controls whether or not the DCO
frequency range is narrowed to its maximum frequency with a 32.768 kHz reference. See Table 11-7.
0 DCO has default range of 25%.
1 DCO is fined tuned for maximum frequency with 32.768 kHz reference.
4
IREFST
Internal Reference Status — The IREFST bit indicates the current source for the reference clock. The IREFST
bit does not update immediately after a write to the IREFS bit due to internal synchronization between clock
domains.
0 Source of reference clock is external clock.
1 Source of reference clock is internal clock.
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