Data Mapping UM353-1
March 2003
7-8
7.3.2 Variable Loop Integer Data
Controller [ODC]
Code R/W Description Range Register (MB) C/P (LIL)
L#TSPI
R/W
Target Setpoint (%)
-3.3 to 103.3 ($0-$0FFF)
40451+30(#-1)
n+1/2
L#HLI
R/W
Setpoint High Limit (%)
-3.3 to 103.3 ($0-$0FFF)
40452+30(#-1)
n+1/4
L#LLI
R/W
Setpoint Low Limit (%)
-3.3 to 103.3 ($0-$0FFF)
40453+30(#-1)
n+1/5
L#RTI
R/W
Setpoint Ramp Time (min)
0-3840($0080-$0F80)
40454+30(#-1)
n+1/3
L#RRI
R/W
Setpoint Ramp Rate (%/min)
-3.3 to 103.3 ($0-$0FFF)
40455+30(#-1)
n+1/6
L#A1LI
R/W
Alarm 1 Limit (%)
-3.3 to 103.3 ($0-$0FFF)
40456+30(#-1)
n+4/2
L#A2LI
R/W
Alarm 2 Limit (%)
-3.3 to 103.3 ($0-$0FFF)
40457+30(#-1)
n+4/3
L#A3LI
R/W
Alarm 3 Limit (%)
-3.3 to 103.3 ($0-$0FFF)
40458+30(#-1)
n+4/4
L#A4LI
R/W
Alarm 4 Limit (%)
-3.3 to 103.3 ($0-$0FFF)
40459+30(#-1)
n+4/5
L#T1mI
R/W
Tot. Preset 1 - 3 ms whole digits
0-999 ($0000-$03E7)
40460+30(#-1)
n+2/4
L#T1lI
R/W
Tot. Preset 1 - 3 ls whole digits
0-999 ($0000-$03E7)
40461+30(#-1)
n+2/5
L#T2mI R/W Tot. Preset 2 - 3 ms whole digits 0-999 ($0000-$03E7) 404621+30(#-1) n+2/6
L#T2lI R/W Tot. Preset 2 - 3 ls whole digits 0-999 ($0000-$03E7) 40463+30(#-1) n+2/7
L#A1TW R/W Alarm 1 Type Word (bit mapped - see ATW) n/a n+4/6
L#A2TW R/W Alarm 2 Type Word (bit mapped - see ATW) n/a n+4/7
L#A3TW R/W Alarm 3 Type Word (bit mapped - see ATW) n/a n+4/8
L#A4TW R/W Alarm 4 Type Word (bit mapped - see ATW) n/a n+4/9
L#A1TI R/W Alarm 1 Type 0-6 ($0000-$0006) 40464+30(#-1) n+4/37
L#A2TI R/W Alarm 2 Type 0-6 ($0000-$0006) 40465+30(#-1) n+4/38
L#A3TI R/W Alarm 3 Type 0-6 ($0000-$0006) 40466+30(#-1) n+4/39
L#A4TI R/W Alarm 4 Type 0-6 ($0000-$0006) 40467+30(#-1) n+4/40
L#A1PI R/W Alarm 1 Priority 1-5 ($0001-$0005) 40468+30(#-1) n+4/41
L#A2PI R/W Alarm 2 Priority 1-5 ($0001-$0005) 40469+30(#-1) n+4/42
L#A3PI R/W Alarm 3 Priority 1-5 ($0001-$0005) 40470+30(#-1) n+4/43
L#A4PI R/W Alarm 4 Priority 1-5 ($0001-$0005) 40471+30(#-1) n+4/44
L#CAI R/W Controller Action 1-DIR, 0-REV 40472+30(#-1) n+1/7
(spare) 0 ($0000) 40473+30(#-1)
….. ….. ….. ….. ….. …..
(spare) 0 ($0000) 40480+30(#-1)
Sequencer [ODS] - (MASK Configurations)
Code R/W Description Range Register (MB) C/P (LIL)
L#S001G0I R/W Step 1 Group 0 Input Mask $0000-$FFFF 40451+30(#-1) 1/154
L#S001G0O R/W Step 1 Group 0 Output Mask $0000-$FFFF 40452+30(#-1) 1/170
L#S001G1I R/W Step 1 Group 1 Input Mask $0000-$FFFF 40453+30(#-1) 1/155
L#S001G1O R/W Step 1 Group 1 Output Mask $0000-$FFFF 40454+30(#-1) 1/171
L#S001G2I R/W Step 1 Group 2 Input Mask $0000-$FFFF 40455+30(#-1) 1/156
L#S001G2O R/W Step 1 Group 2 Output Mask $0000-$FFFF 40456+30(#-1) 1/172
L#S002G0I R/W Step 2 Group 0 Input Mask $0000-$FFFF 40457+30(#-1) 2/154
L#S002G0O R/W Step 2 Group 0 Output Mask $0000-$FFFF 40458+30(#-1) 2/170
….. ….. ….. ….. ….. …..
L#S005G0O R/W Step 5 Group 0 Output Mask $0000-$FFFF 40476+30(#-1) 5/170
L#S005G1I R/W Step 5 Group 1 Input Mask $0000-$FFFF 40477+30(#-1) 5/155
L#S005G1O R/W Step 5 Group 1 Output Mask $0000-$FFFF 40478+30(#-1) 5/171
L#S005G2I R/W Step 5 Group 2 Input Mask $0000-$FFFF 40479+30(#-1) 5/156
L#S005G2O R/W Step 5 Group 2 Output Mask $0000-$FFFF 40480+30(#-1) 5/172
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