Siemens Simatic S7-1500 CPU 1512C-1 PN - Page 49

Technology functions
3.1 High-speed counters
CPU 1512C-1 PN (6ES7512-1CK01-0AB0)
Manual, 12/2017, A5E40898741-AA
49
Offset from start
address
Parameter
Meaning
Byte 10
SET_DIR
Bit 7: Count direction (with encoder without direction signal)
– Bits 2 to 6: Reserve; bits must be set to 0
RES_EVENT
Bit 1: Reset of saved events
RES_ERROR
Bit 0: Reset of saved error states
Byte 11
–
Bits 0 to 7: Reserve; bits must be set to 0
* If values are l
oaded simultaneously via LD_SLOT_0 and LD_SLOT_1, the value from Slot 0 is taken first internally and
then the value from Slot 1 . This may lead to unexpected intermediate states.
Reference
You can find a graphic representation of the processing of the various SLOT parameters in
the section Handling the SLOT parameter (control interface) (Page 71).