DSP BOARD IC5202 ADSST-AVR-1131 (DSP2)
Pin No. Pin Name I/O Description
A1
CLKCFG0 I Clock frequency setting terminal
XTAL O System clock output terminal (25 MHz)
MOSI I/O
When DSP2 is master: Serial data output to the serial flash
When DSP2 is slave: Serial data input from the DSP controller
MISO I/O
When DSP2 is master: Serial data input from the serial flash
When DSP2 is slave: Serial data output to the DSP controller
SPIDS I Serial data latch pulse signal input from the DSP controller
VDDINT - Power supply terminal (+1.2V)
CLKCFG1 I Clock frequency setting terminal
VDDEXT - Power supply terminal (+3.3V)
CLKIN I System clock input terminal (25 MHz)
AVDD - Power supply terminal (+1.2V)
VDDEXT - Power supply terminal (+3.3V)
SPICLK I/O
When DSP2 is master: Serial data transfer clock signal input from the DSP controller
When DSP2 is slave: Serial data transfer clock signal output to the serial flash
RESET I Reset signal input from the DSP controller "L": reset
VDDINT - Power supply terminal (+1.2V)
BOOTCFG1,
BOOTCFG0
I Boot mode setting signal input from the DSP controller
C3, C12,
C13
GND - Ground terminal
VDDINT - Power supply terminal (+1.2V)
D2, D4 to
D6, D9 to
D11, D13
GND - Ground terminal
VDDINT - Power supply terminal (+1.2V)
E2, E4 to
E6, E9 to
E11, E13
GND - Ground terminal
SF2_DSP2_CE O Chip enable signal output to the serial flash
FLAG1 I
Audio muting control signal input from the digital audio interface receiver, video system controller
or HDMI receiver
FLAG0 O Interrupt request signal output to the DSP controller
F4 to F6,
F9 to F11
GND - Ground terminal
P_ERROR I PLL lock error signal and data error flag input from the DSP1
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