Sony STR-DA5300ES - Page 146

146
STR-DA5300ES
DSP BOARD IC5208 MB91F353APMT-07A53DSP-X103 (DSP CONTROLLER)
Pin No. Pin Name I/O Description
1
RDATA0 I Audio serial data input from the digital audio interface receiver
2 to 8 - -
Not used
9
DSP2_SIB_SEL O Data selection signal output to the data selector
10
P_ERROR I PLL lock error signal and data error flag input from the DSP1
11
DSP1_SPIDS O Serial data latch pulse signal output to the DSP1
12
DSP1_RESET O Reset signal output to the DSP1 and flash memory "L": reset
13, 14
DSP1_
BOOTCFG0,
DSP1_
BOOTCFG1
O Boot mode setting signal output to the DSP1
15, 16 - -
Not used
17 SF2_DSP2_MAS I
Master/slave selection signal input from the DSP2
18, 19 - -
Not used
20
SF2_CPU_CE O Chip enable signal output to the serial flash
21
DSP2_SPIDS O Serial data latch pulse signal output to the DSP2
22
DSP2_RESET O Reset signal output to the DSP2 "L": reset
23, 24 - -
Not used
25, 26
DSP2_
BOOTCFG0,
DSP2_
BOOTCFG1
O Boot mode setting signal output to the DSP2
27 to 35 - -
Not used
36
DRST_TRG I Programming end flag input from the system controller
37 to 39 - -
Not used
40
VSS - Ground terminal
41, 42 - -
Not used
43
VSS - Ground terminal
44
VCC - Power supply terminal (+3.3V)
45 to 47 - -
Not used
48
RD
-
Not used
49 WR0 -
Not used
50, 51 - -
Not used
52
MD2 I Programming mode signal input from the system controller
53, 54
MD1, MD0 I Programming mode signal input terminal Not used
55
XRESET I Reset signal input from the system controller "L": reset
56
VCC - Power supply terminal (+3.3V)
57
XOUT O System clock output terminal (12.5 MHz)
58
XIN I System clock input terminal (12.5 MHz)
59
VSS - Ground terminal
60 to 62 - -
Not used
63
MD_BUSY I Busy signal input from the system controller
64
DM_BUSY O Busy signal output to the system controller
65 DM_INT
O Interrupt request signal output terminal Not used
66 to 69 - -
Not used
70, 71 PN0, PN2 -
Not used
72 to 75 - -
Not used
76
VSS - Ground terminal