The STM32 Cortex-M4 instruction set PM0214
84/262 PM0214 Rev 9
Restrictions
In these instructions:
• Operand2 must be neither SP nor PC
• Rd can be SP only in ADD and SUB, and only with the following additional restrictions:
– Rn must also be SP.
– Any shift in operand2 must be limited to a maximum of three bits using LSL.
• Rn can be SP only in ADD and SUB.
• Rd can be PC only in the ADD{cond} PC, PC, Rm instruction where:
– You must not specify the S suffix.
– Rm must be neither PC nor SP.
– If the instruction is conditional, it must be the last instruction in the IT block.
• With the exception of the ADD{cond} PC, PC, Rm instruction, Rn can be PC only in
ADD and SUB, and only with the following additional restrictions:
– You must not specify the S suffix.
– The second operand must be a constant in the range 0 to 4095.
Note: 1 When using the PC for an addition or a subtraction, bits[1:0] of the PC are rounded to b00
before performing the calculation, making the base address for the calculation word-aligned.
2 If you want to generate the address of an instruction, you have to adjust the constant based
on the value of the PC. Arm recommends that you use the
ADR
instruction instead of
ADD
or
SUB
with
Rn
equal to the PC, because your assembler automatically calculates the correct
constant for the
ADR
instruction.
When Rd is PC in the ADD{cond} PC, PC, Rm instruction:
• Bit[0] of the value written to the PC is ignored.
• A branch occurs to the address created by forcing bit[0] of that value to 0.
Condition flags
If
S
is specified, these instructions update the N, Z, C and V flags according to the result.
Examples
ADD R2, R1, R3
SUBS R8, R6, #240 ; sets the flags on the result
RSB R4, R4, #1280 ; subtracts contents of R4 from 1280
ADCHI R11, R0, R3 ; only executed if C flag set and Z flag clear
Multiword arithmetic examples
Specific example 4: 64-bit addition shows two instructions that add a 64-bit integer
contained in R2 and R3 to another 64-bit integer contained in R0 and R1, and place the
result in R4 and R5.
Specific example 4: 64-bit addition
ADDS R4, R0, R2 ; add the least significant words
ADC R5, R1, R3 ; add the most significant words with carry
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