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Tandy 1000 Technical Reference Manual

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Tandy 1000
Technical Reference Manual
8272A
NAME
8272A REGISTERS -
CPU
INTERFACE
Note: Design must guarantee that the 8272A
is not subjected
to
illegal inputs.
The
010
and ROM
bits
in
the
Status
Register
indicate
when
Data
is
ready
and
in
which
direction
data
will
be
transferred
on the
Data
Bus.
Note: There is a
121'5
or
241'5
ROM
flag delay when
using
an
8 or 4 MHz clock respectively.
JrljOTES
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DATA
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IlEA.OV
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~:6~::SQ~:HIII
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~:6~EA:sa~:HR
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READV
FO" IolUT
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10
BE
REAO
IV
Figure
5.
Status
Register
Timing
DATA
",~~
0"'0'
,"OC''''''
A'D
,"'0
'DC
or
0'
'OC
AND
,"TO
,"oC"'L
'EAD'
I I
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,"OMI
I
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I I I ! I I I i I
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I A I • I
1.1
A I c I 0 I c
101.1
A I
The 8272A
is
capable
of
executing
15
different
com-
mands.
Each
command
is
initiated
by a mUlti-byte
transfer
from
the
proceS'lor,
and
the
result
after
execu-
tion
of
the
command
may
also
be a
multi-byte
transfer
back
to
the processor.
Because
of
this
multi·byte
inter-
change
of
information
between
the
8272A and
the
proc-
essor,
it
is
convenient
to
consider
each
command
as
consisting
of
three
phases:
Command
Phase:
The
FOG
receives
all
information
required
to
perform
a
particular
operation
from
the
processor
Execution
Phase:
The
FDC
performs
the
operation
it
was
instructed
to
do
Result
Phase
After
completion
of
the
operation,
status
and
other
housekeeping
in-
formation
are made available
to
the
processor.
During
Command
or
Result
Phases
tM
Main
Status
Register
(described
in
Table
3)
must
be read
by
the proc-
essor
before
each
byte
of
information
is
written
into
or
read
from
the Data
Register.
Bits
06
and
07
in the Main
Status
Register
must
be
in a a
and
1
state,
respectively,
before
each
byte
of
the
command
word
may
be
written
into
the
8272A.
Many
of
the
commands
require
multiple
bytes,
and
as
a result
the
Main
Status
Register
must
be
read
prior
to
each
byte
transfer
to
the
8272A. On
the
other
hand,
during
the
Result
Phase,
06
and
07
in
the
Main
Status
Register
must
both
be
1's
(06
= 1 and
07
=
1)
before
reading
each
byte
from the
Data
Register.
Note,
this
reading
of
the
Main
Status
Register
before
each
byte
transfer
to
the
8272A
is
required in
only
the
Command
and
Result
Phases,
and
NOT
during
the
Execution
Phase.
During
the
Execution
Phase,
the
Main
Status
Register
need
not
be read. If
the
8272A
is
in
the
non-DMA
Mode,
then
the
receipt
of
each
data
byte
(if 8272A is
reading,
data
from
FDD) is
indicated
by an
Interrupt
signal
on
pin
18 (INT =
1).
The
generation
of
a Read
signal
(RD =
0)
will
reset
the
Interrupt
as
well
as
output
the
Data
onto
A
read
or
write
command
is
In
process
The
Foe
is
in
Ihe
non·DMA
mode
ThiSbl!
IS
set
only
dur
Inglheexecutionphasetn
non-DMA
mode.
Transition
to
O"slaleindicalesexecu!lon
phase
has
ended
Indicates
direction
01
data
transler
between
FOC
and
Dt
Register
II
QIO=""'lhen
transfer
is
from
Data
Register
to
the
Processor
11010="0
then
transfer
is
trom
the
Proc
eSSOf
to
Data
Reglsler
O,S
~~~enumber
1
is
In
the
Seek
DOB
~~~enumber
0 IS
in
the
Seek
°0
FOOD
Busy
0,
FDD
1
Busy
°2
FDD
2
Busy
0)
FDD 3
Busy
0,
Foe
Busy
°5
°6
Data
InpuliOulput
0,
Request
for
Master
A
o
AD
WR
FUNCTION
0 0
1
Read
Main
Status
Register
0
1
0
Illegal
(see note)
0 0
0
Illegal
(see note)
1
0 0
Illegal
(see note)
1
0
1
Read
from
Data
Register
1
1 1
Write
into
Data
Register
Indicates
Dala
Register
is
ready
to
send
or
receive
data
10
Of
from
the
Processor
80t
bits
010
and
AOM
should
be
used
10
perform
the
hand
shaking
funcllons
of
"ready
and
"direction"
10
the
PfOC
The
relationship
between
the
StatuslData
registers
and
the
signals
RD,
WR,
and
A
o
is
shown
in Table
2.
Table
2.
AQ,
RD,
WR
decoding
for
the
selection
of
Status/Data
register
functions.
The
Main
Status
Register
bits
are
defined
in
Table
3.
Table
3.
Main
Status
Register
bit
description.
The 8272A
contains
two
registers
which
may
be ac·
cessed
by
the
main
system
processor;
a
Status
Register
and
a
Data
Register.
The 8-bit
Main
Status
Register
con-
tains
the
status
information
of
the
FDC,
and
may
be
accessed
at
any
time.
The 8-bit
Data
Register
(actually
consists
of
several
registers
in a
stack
with
only
one
register
presented
to
the
data
bus
at a time),
stores
data,
commands,
parameters,
and FDD
status
informa-
tion.
Data
bytes
are read
out
of, or
written
into,
the
Data
Register
in
order
to
program
or
obtain
the
results
after
execution
of
a
command.
The
Status
Register
may
only
be read
and
is
used
to
facilitate
the
transfer
of
data
between
the
processor
and 8272A.
6-227

Table of Contents

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Preview: User Guide
User Guide337 pages
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Programmer's Reference Guide251 pages
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Basic Reference Manual411 pages
Preview: Owner's Manual
Owner's Manual46 pages

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Tandy 1000 Specifications

General IconGeneral
ProcessorIntel 8088
Processor Speed4.77 MHz
RAM128 KB (expandable to 640 KB)
Operating SystemMS-DOS 2.11
ManufacturerTandy Corporation
Release Year1984
StorageSingle or double 5.25" floppy disk drive (360 KB), optional hard drive
SoundTandy 3-voice sound
PortsParallel, Serial
GraphicsCGA (Color Graphics Adapter)
Graphics Modes320x200, 640x200

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