LE910Cx Hardware Design Guide
1VV0301298 Rev.40 Page 62 of 149 2023-03-16
Not Subject to NDA
Note that this is not done in order to avoid RF power loss but to avoid voltage drops
on the power line at the current peaks frequency of 216 Hz that will reflect on all
the components connected to this supply (also introducing the noise floor at the
burst base frequency)
For this reason, while a voltage drop of 300-400 mV may be acceptable from the
RF power loss point of view, the same voltage drop may not be acceptable from
the noise point of view. If the application does not have an audio interface but only
uses the data feature of the LE910Cx, this noise is not so disturbing, and the power
supply layout design can be more forgiving.
The PCB traces to LE910Cx and the bypass capacitor must be wide enough to
ensure that no significant voltage drops occur when the 2A current peaks are
absorbed. This is needed for the same above-mentioned reasons. Try to keep
these traces as short as possible.
The PCB traces connecting the switching output to the inductor must be inductive
and not capacitive, so keep it short and not too wide placing the inductor the
closest you can to the power switching IC (only for the switching power supply).
This is done also to slightly improve efficiency but mainly to reduce the radiated
field (noise).
Use a good common ground plane, (some exception to this general rule can be
done for the DCDC Power GND return path, according to DCDC vendor suggestions
(the return path of the input capacitor should not be on the main ground plane, it
should be routed with a short track directly to the ball of the Vss of the regulator).
Place the power supply on the board ensuring that the high current return paths
in the ground plane do not overlap any noise sensitive circuitry, such as the
microphone amplifier/buffer or earphone amplifier.
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